/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef DPE_IPPRIV_H
#define DPE_IPPRIV_H

#ifdef __cplusplus
extern "C" {
#endif

/*!
 * @addtogroup DPE Register Masks
 * @{
 */

/** register DPE_VCAN_TX_PACKET_ADDR offset */
#define DPE_VCAN_TX_PACKET_ADDR_OFFSET(x)                                      (0x0U + (0x80U * (x)))

/* DPE_VCAN_TX_PACKET_ADDR_SRC_ADDR Bit Fields */
#define DPE_VCAN_TX_PACKET_ADDR_SRC_ADDR_MASK                                  (0x1FFFFFFFU)
#define DPE_VCAN_TX_PACKET_ADDR_SRC_ADDR_SHIFT                                 (0U)
#define DPE_VCAN_TX_PACKET_ADDR_SRC_ADDR_WIDTH                                 (29U)
#define DPE_VCAN_TX_PACKET_ADDR_SRC_ADDR(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_PACKET_ADDR_SRC_ADDR_SHIFT)) & DPE_VCAN_TX_PACKET_ADDR_SRC_ADDR_MASK)

/* DPE_VCAN_TX_PACKET_ADDR_PACKET_SEND Bit Fields */
#define DPE_VCAN_TX_PACKET_ADDR_PACKET_SEND_MASK                               (0x80000000U)
#define DPE_VCAN_TX_PACKET_ADDR_PACKET_SEND_SHIFT                              (31U)
#define DPE_VCAN_TX_PACKET_ADDR_PACKET_SEND_WIDTH                              (1U)
#define DPE_VCAN_TX_PACKET_ADDR_PACKET_SEND(x)                                 (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_PACKET_ADDR_PACKET_SEND_SHIFT)) & DPE_VCAN_TX_PACKET_ADDR_PACKET_SEND_MASK)

/** register DPE_VCAN_TX_FIFO_STATUS offset */
#define DPE_VCAN_TX_FIFO_STATUS_OFFSET(x)                                      (0x4U + (0x80U * (x)))

/* DPE_VCAN_TX_FIFO_STATUS_FIFO_FULL Bit Fields */
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_FULL_MASK                                 (0x1U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_FULL_SHIFT                                (0U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_FULL_WIDTH                                (1U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_FULL(x)                                   (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_FIFO_STATUS_FIFO_FULL_SHIFT)) & DPE_VCAN_TX_FIFO_STATUS_FIFO_FULL_MASK)

/* DPE_VCAN_TX_FIFO_STATUS_FIFO_EMPTY Bit Fields */
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_EMPTY_MASK                                (0x2U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_EMPTY_SHIFT                               (1U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_EMPTY_WIDTH                               (1U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_EMPTY(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_FIFO_STATUS_FIFO_EMPTY_SHIFT)) & DPE_VCAN_TX_FIFO_STATUS_FIFO_EMPTY_MASK)

/* DPE_VCAN_TX_FIFO_STATUS_FIFO_FLUSH Bit Fields */
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_FLUSH_MASK                                (0x4U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_FLUSH_SHIFT                               (2U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_FLUSH_WIDTH                               (1U)
#define DPE_VCAN_TX_FIFO_STATUS_FIFO_FLUSH(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_FIFO_STATUS_FIFO_FLUSH_SHIFT)) & DPE_VCAN_TX_FIFO_STATUS_FIFO_FLUSH_MASK)

/* DPE_VCAN_TX_FIFO_STATUS_VCAN_TX_FIFO_ENTRIES Bit Fields */
#define DPE_VCAN_TX_FIFO_STATUS_VCAN_TX_FIFO_ENTRIES_MASK                      (0x1F00U)
#define DPE_VCAN_TX_FIFO_STATUS_VCAN_TX_FIFO_ENTRIES_SHIFT                     (8U)
#define DPE_VCAN_TX_FIFO_STATUS_VCAN_TX_FIFO_ENTRIES_WIDTH                     (5U)
#define DPE_VCAN_TX_FIFO_STATUS_VCAN_TX_FIFO_ENTRIES(x)                        (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_FIFO_STATUS_VCAN_TX_FIFO_ENTRIES_SHIFT)) & DPE_VCAN_TX_FIFO_STATUS_VCAN_TX_FIFO_ENTRIES_MASK)

/** register DPE_VCAN_CTRL offset */
#define DPE_VCAN_CTRL_OFFSET(x)                                                (0x8U + (0x80U * (x)))

/* DPE_VCAN_CTRL_EN Bit Fields */
#define DPE_VCAN_CTRL_EN_MASK                                                  (0x1U)
#define DPE_VCAN_CTRL_EN_SHIFT                                                 (0U)
#define DPE_VCAN_CTRL_EN_WIDTH                                                 (1U)
#define DPE_VCAN_CTRL_EN(x)                                                    (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_CTRL_EN_SHIFT)) & DPE_VCAN_CTRL_EN_MASK)

/* DPE_VCAN_CTRL_RETRY_DROP_EN Bit Fields */
#define DPE_VCAN_CTRL_RETRY_DROP_EN_MASK                                       (0x2U)
#define DPE_VCAN_CTRL_RETRY_DROP_EN_SHIFT                                      (1U)
#define DPE_VCAN_CTRL_RETRY_DROP_EN_WIDTH                                      (1U)
#define DPE_VCAN_CTRL_RETRY_DROP_EN(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_CTRL_RETRY_DROP_EN_SHIFT)) & DPE_VCAN_CTRL_RETRY_DROP_EN_MASK)

/* DPE_VCAN_CTRL_RETRY_DROP_CNT_CLR Bit Fields */
#define DPE_VCAN_CTRL_RETRY_DROP_CNT_CLR_MASK                                  (0x4U)
#define DPE_VCAN_CTRL_RETRY_DROP_CNT_CLR_SHIFT                                 (2U)
#define DPE_VCAN_CTRL_RETRY_DROP_CNT_CLR_WIDTH                                 (1U)
#define DPE_VCAN_CTRL_RETRY_DROP_CNT_CLR(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_CTRL_RETRY_DROP_CNT_CLR_SHIFT)) & DPE_VCAN_CTRL_RETRY_DROP_CNT_CLR_MASK)

/* DPE_VCAN_CTRL_RETRY_DROPPED_CNT Bit Fields */
#define DPE_VCAN_CTRL_RETRY_DROPPED_CNT_MASK                                   (0xFF00U)
#define DPE_VCAN_CTRL_RETRY_DROPPED_CNT_SHIFT                                  (8U)
#define DPE_VCAN_CTRL_RETRY_DROPPED_CNT_WIDTH                                  (8U)
#define DPE_VCAN_CTRL_RETRY_DROPPED_CNT(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_CTRL_RETRY_DROPPED_CNT_SHIFT)) & DPE_VCAN_CTRL_RETRY_DROPPED_CNT_MASK)

/** register DPE_VCAN_RX_PACKET_ADDR offset */
#define DPE_VCAN_RX_PACKET_ADDR_OFFSET(x)                                      (0x10U + (0x80U * (x)))

/* DPE_VCAN_RX_PACKET_ADDR_VCAN_FRIST_VALID_PACKET_INDEX Bit Fields */
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_FRIST_VALID_PACKET_INDEX_MASK             (0xFU)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_FRIST_VALID_PACKET_INDEX_SHIFT            (0U)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_FRIST_VALID_PACKET_INDEX_WIDTH            (4U)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_FRIST_VALID_PACKET_INDEX(x)               (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_RX_PACKET_ADDR_VCAN_FRIST_VALID_PACKET_INDEX_SHIFT)) & DPE_VCAN_RX_PACKET_ADDR_VCAN_FRIST_VALID_PACKET_INDEX_MASK)

/* DPE_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX Bit Fields */
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_MASK                 (0xF00U)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_SHIFT                (8U)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_WIDTH                (4U)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX(x)                   (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_SHIFT)) & DPE_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_MASK)

/* DPE_VCAN_RX_PACKET_ADDR_VCAN_RX_RD_PTR_INDEX Bit Fields */
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_RX_RD_PTR_INDEX_MASK                      (0xF0000U)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_RX_RD_PTR_INDEX_SHIFT                     (16U)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_RX_RD_PTR_INDEX_WIDTH                     (4U)
#define DPE_VCAN_RX_PACKET_ADDR_VCAN_RX_RD_PTR_INDEX(x)                        (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_RX_PACKET_ADDR_VCAN_RX_RD_PTR_INDEX_SHIFT)) & DPE_VCAN_RX_PACKET_ADDR_VCAN_RX_RD_PTR_INDEX_MASK)

/* DPE_VCAN_RX_PACKET_ADDR_PACKET_POP Bit Fields */
#define DPE_VCAN_RX_PACKET_ADDR_PACKET_POP_MASK                                (0x80000000U)
#define DPE_VCAN_RX_PACKET_ADDR_PACKET_POP_SHIFT                               (31U)
#define DPE_VCAN_RX_PACKET_ADDR_PACKET_POP_WIDTH                               (1U)
#define DPE_VCAN_RX_PACKET_ADDR_PACKET_POP(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_RX_PACKET_ADDR_PACKET_POP_SHIFT)) & DPE_VCAN_RX_PACKET_ADDR_PACKET_POP_MASK)

/** register DPE_VCAN_RX_FIFO_STATUS offset */
#define DPE_VCAN_RX_FIFO_STATUS_OFFSET(x)                                      (0x14U + (0x80U * (x)))

/* DPE_VCAN_RX_FIFO_STATUS_FIFO_FULL Bit Fields */
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_FULL_MASK                                 (0x1U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_FULL_SHIFT                                (0U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_FULL_WIDTH                                (1U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_FULL(x)                                   (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_RX_FIFO_STATUS_FIFO_FULL_SHIFT)) & DPE_VCAN_RX_FIFO_STATUS_FIFO_FULL_MASK)

/* DPE_VCAN_RX_FIFO_STATUS_FIFO_EMPTY Bit Fields */
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_MASK                                (0x2U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_SHIFT                               (1U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_WIDTH                               (1U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_EMPTY(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_SHIFT)) & DPE_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_MASK)

/* DPE_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES Bit Fields */
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_MASK                              (0x1F00U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_SHIFT                             (8U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_WIDTH                             (5U)
#define DPE_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES(x)                                (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_SHIFT)) & DPE_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_MASK)

/** register DPE_VCAN_RX_FIFO_CONFIG offset */
#define DPE_VCAN_RX_FIFO_CONFIG_OFFSET(x)                                      (0x18U + (0x80U * (x)))

/* DPE_VCAN_RX_FIFO_CONFIG_VCAN_RX_FIFO_START_ADDR Bit Fields */
#define DPE_VCAN_RX_FIFO_CONFIG_VCAN_RX_FIFO_START_ADDR_MASK                   (0xFFFFFFF8U)
#define DPE_VCAN_RX_FIFO_CONFIG_VCAN_RX_FIFO_START_ADDR_SHIFT                  (3U)
#define DPE_VCAN_RX_FIFO_CONFIG_VCAN_RX_FIFO_START_ADDR_WIDTH                  (29U)
#define DPE_VCAN_RX_FIFO_CONFIG_VCAN_RX_FIFO_START_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_RX_FIFO_CONFIG_VCAN_RX_FIFO_START_ADDR_SHIFT)) & DPE_VCAN_RX_FIFO_CONFIG_VCAN_RX_FIFO_START_ADDR_MASK)

/** register DPE_VCANINTEN offset */
#define DPE_VCANINTEN_OFFSET(x)                                                (0x20U + (0x80U * (x)))

/* DPE_VCANINTEN_VCAN_REC Bit Fields */
#define DPE_VCANINTEN_VCAN_REC_MASK                                            (0x1U)
#define DPE_VCANINTEN_VCAN_REC_SHIFT                                           (0U)
#define DPE_VCANINTEN_VCAN_REC_WIDTH                                           (1U)
#define DPE_VCANINTEN_VCAN_REC(x)                                              (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTEN_VCAN_REC_SHIFT)) & DPE_VCANINTEN_VCAN_REC_MASK)

/* DPE_VCANINTEN_VCAN_REC_DROP Bit Fields */
#define DPE_VCANINTEN_VCAN_REC_DROP_MASK                                       (0x2U)
#define DPE_VCANINTEN_VCAN_REC_DROP_SHIFT                                      (1U)
#define DPE_VCANINTEN_VCAN_REC_DROP_WIDTH                                      (1U)
#define DPE_VCANINTEN_VCAN_REC_DROP(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTEN_VCAN_REC_DROP_SHIFT)) & DPE_VCANINTEN_VCAN_REC_DROP_MASK)

/* DPE_VCANINTEN_VCAN_SEND_DONE Bit Fields */
#define DPE_VCANINTEN_VCAN_SEND_DONE_MASK                                      (0x4U)
#define DPE_VCANINTEN_VCAN_SEND_DONE_SHIFT                                     (2U)
#define DPE_VCANINTEN_VCAN_SEND_DONE_WIDTH                                     (1U)
#define DPE_VCANINTEN_VCAN_SEND_DONE(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTEN_VCAN_SEND_DONE_SHIFT)) & DPE_VCANINTEN_VCAN_SEND_DONE_MASK)

/* DPE_VCANINTEN_VCAN_SEND_TIMEOUT Bit Fields */
#define DPE_VCANINTEN_VCAN_SEND_TIMEOUT_MASK                                   (0x8U)
#define DPE_VCANINTEN_VCAN_SEND_TIMEOUT_SHIFT                                  (3U)
#define DPE_VCANINTEN_VCAN_SEND_TIMEOUT_WIDTH                                  (1U)
#define DPE_VCANINTEN_VCAN_SEND_TIMEOUT(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTEN_VCAN_SEND_TIMEOUT_SHIFT)) & DPE_VCANINTEN_VCAN_SEND_TIMEOUT_MASK)

/* DPE_VCANINTEN_VCAN_SEND_DROP Bit Fields */
#define DPE_VCANINTEN_VCAN_SEND_DROP_MASK                                      (0x10U)
#define DPE_VCANINTEN_VCAN_SEND_DROP_SHIFT                                     (4U)
#define DPE_VCANINTEN_VCAN_SEND_DROP_WIDTH                                     (1U)
#define DPE_VCANINTEN_VCAN_SEND_DROP(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTEN_VCAN_SEND_DROP_SHIFT)) & DPE_VCANINTEN_VCAN_SEND_DROP_MASK)

/** register DPE_VCANINTSTAT offset */
#define DPE_VCANINTSTAT_OFFSET(x)                                              (0x24U + (0x80U * (x)))

/* DPE_VCANINTSTAT_VCAN_REC Bit Fields */
#define DPE_VCANINTSTAT_VCAN_REC_MASK                                          (0x1U)
#define DPE_VCANINTSTAT_VCAN_REC_SHIFT                                         (0U)
#define DPE_VCANINTSTAT_VCAN_REC_WIDTH                                         (1U)
#define DPE_VCANINTSTAT_VCAN_REC(x)                                            (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTSTAT_VCAN_REC_SHIFT)) & DPE_VCANINTSTAT_VCAN_REC_MASK)

/* DPE_VCANINTSTAT_VCAN_REC_DROP Bit Fields */
#define DPE_VCANINTSTAT_VCAN_REC_DROP_MASK                                     (0x2U)
#define DPE_VCANINTSTAT_VCAN_REC_DROP_SHIFT                                    (1U)
#define DPE_VCANINTSTAT_VCAN_REC_DROP_WIDTH                                    (1U)
#define DPE_VCANINTSTAT_VCAN_REC_DROP(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTSTAT_VCAN_REC_DROP_SHIFT)) & DPE_VCANINTSTAT_VCAN_REC_DROP_MASK)

/* DPE_VCANINTSTAT_VCAN_SEND_DONE Bit Fields */
#define DPE_VCANINTSTAT_VCAN_SEND_DONE_MASK                                    (0x4U)
#define DPE_VCANINTSTAT_VCAN_SEND_DONE_SHIFT                                   (2U)
#define DPE_VCANINTSTAT_VCAN_SEND_DONE_WIDTH                                   (1U)
#define DPE_VCANINTSTAT_VCAN_SEND_DONE(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTSTAT_VCAN_SEND_DONE_SHIFT)) & DPE_VCANINTSTAT_VCAN_SEND_DONE_MASK)

/* DPE_VCANINTSTAT_VCAN_SEND_TIMEOUT Bit Fields */
#define DPE_VCANINTSTAT_VCAN_SEND_TIMEOUT_MASK                                 (0x8U)
#define DPE_VCANINTSTAT_VCAN_SEND_TIMEOUT_SHIFT                                (3U)
#define DPE_VCANINTSTAT_VCAN_SEND_TIMEOUT_WIDTH                                (1U)
#define DPE_VCANINTSTAT_VCAN_SEND_TIMEOUT(x)                                   (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTSTAT_VCAN_SEND_TIMEOUT_SHIFT)) & DPE_VCANINTSTAT_VCAN_SEND_TIMEOUT_MASK)

/* DPE_VCANINTSTAT_VCAN_SEND_DROP Bit Fields */
#define DPE_VCANINTSTAT_VCAN_SEND_DROP_MASK                                    (0x10U)
#define DPE_VCANINTSTAT_VCAN_SEND_DROP_SHIFT                                   (4U)
#define DPE_VCANINTSTAT_VCAN_SEND_DROP_WIDTH                                   (1U)
#define DPE_VCANINTSTAT_VCAN_SEND_DROP(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTSTAT_VCAN_SEND_DROP_SHIFT)) & DPE_VCANINTSTAT_VCAN_SEND_DROP_MASK)

/** register DPE_VCANINTCLR offset */
#define DPE_VCANINTCLR_OFFSET(x)                                               (0x28U + (0x80U * (x)))

/* DPE_VCANINTCLR_VCAN_REC Bit Fields */
#define DPE_VCANINTCLR_VCAN_REC_MASK                                           (0x1U)
#define DPE_VCANINTCLR_VCAN_REC_SHIFT                                          (0U)
#define DPE_VCANINTCLR_VCAN_REC_WIDTH                                          (1U)
#define DPE_VCANINTCLR_VCAN_REC(x)                                             (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTCLR_VCAN_REC_SHIFT)) & DPE_VCANINTCLR_VCAN_REC_MASK)

/* DPE_VCANINTCLR_VCAN_REC_DROP Bit Fields */
#define DPE_VCANINTCLR_VCAN_REC_DROP_MASK                                      (0x2U)
#define DPE_VCANINTCLR_VCAN_REC_DROP_SHIFT                                     (1U)
#define DPE_VCANINTCLR_VCAN_REC_DROP_WIDTH                                     (1U)
#define DPE_VCANINTCLR_VCAN_REC_DROP(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTCLR_VCAN_REC_DROP_SHIFT)) & DPE_VCANINTCLR_VCAN_REC_DROP_MASK)

/* DPE_VCANINTCLR_VCAN_SEND_DONE Bit Fields */
#define DPE_VCANINTCLR_VCAN_SEND_DONE_MASK                                     (0x4U)
#define DPE_VCANINTCLR_VCAN_SEND_DONE_SHIFT                                    (2U)
#define DPE_VCANINTCLR_VCAN_SEND_DONE_WIDTH                                    (1U)
#define DPE_VCANINTCLR_VCAN_SEND_DONE(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTCLR_VCAN_SEND_DONE_SHIFT)) & DPE_VCANINTCLR_VCAN_SEND_DONE_MASK)

/* DPE_VCANINTCLR_VCAN_SEND_TIMEOUT Bit Fields */
#define DPE_VCANINTCLR_VCAN_SEND_TIMEOUT_MASK                                  (0x8U)
#define DPE_VCANINTCLR_VCAN_SEND_TIMEOUT_SHIFT                                 (3U)
#define DPE_VCANINTCLR_VCAN_SEND_TIMEOUT_WIDTH                                 (1U)
#define DPE_VCANINTCLR_VCAN_SEND_TIMEOUT(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTCLR_VCAN_SEND_TIMEOUT_SHIFT)) & DPE_VCANINTCLR_VCAN_SEND_TIMEOUT_MASK)

/* DPE_VCANINTCLR_VCAN_SEND_DROP Bit Fields */
#define DPE_VCANINTCLR_VCAN_SEND_DROP_MASK                                     (0x10U)
#define DPE_VCANINTCLR_VCAN_SEND_DROP_SHIFT                                    (4U)
#define DPE_VCANINTCLR_VCAN_SEND_DROP_WIDTH                                    (1U)
#define DPE_VCANINTCLR_VCAN_SEND_DROP(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_VCANINTCLR_VCAN_SEND_DROP_SHIFT)) & DPE_VCANINTCLR_VCAN_SEND_DROP_MASK)

/** register DPE_VCANCTRL offset */
#define DPE_VCANCTRL_OFFSET(x)                                                 (0x2CU + (0x80U * (x)))

/* DPE_VCANCTRL_STATUS Bit Fields */
#define DPE_VCANCTRL_STATUS_MASK                                               (0xFFFFU)
#define DPE_VCANCTRL_STATUS_SHIFT                                              (0U)
#define DPE_VCANCTRL_STATUS_WIDTH                                              (16U)
#define DPE_VCANCTRL_STATUS(x)                                                 (((uint32_t)(((uint32_t)(x)) << DPE_VCANCTRL_STATUS_SHIFT)) & DPE_VCANCTRL_STATUS_MASK)

/* DPE_VCANCTRL_VCAN_RETRY_INTERVAL Bit Fields */
#define DPE_VCANCTRL_VCAN_RETRY_INTERVAL_MASK                                  (0xFF0000U)
#define DPE_VCANCTRL_VCAN_RETRY_INTERVAL_SHIFT                                 (16U)
#define DPE_VCANCTRL_VCAN_RETRY_INTERVAL_WIDTH                                 (8U)
#define DPE_VCANCTRL_VCAN_RETRY_INTERVAL(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_VCANCTRL_VCAN_RETRY_INTERVAL_SHIFT)) & DPE_VCANCTRL_VCAN_RETRY_INTERVAL_MASK)

/* DPE_VCANCTRL_FREE_SLOT_NUM Bit Fields */
#define DPE_VCANCTRL_FREE_SLOT_NUM_MASK                                        (0x1F000000U)
#define DPE_VCANCTRL_FREE_SLOT_NUM_SHIFT                                       (24U)
#define DPE_VCANCTRL_FREE_SLOT_NUM_WIDTH                                       (5U)
#define DPE_VCANCTRL_FREE_SLOT_NUM(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_VCANCTRL_FREE_SLOT_NUM_SHIFT)) & DPE_VCANCTRL_FREE_SLOT_NUM_MASK)

/* DPE_VCANCTRL_FREE_SLOT_NUM_CLR Bit Fields */
#define DPE_VCANCTRL_FREE_SLOT_NUM_CLR_MASK                                    (0x20000000U)
#define DPE_VCANCTRL_FREE_SLOT_NUM_CLR_SHIFT                                   (29U)
#define DPE_VCANCTRL_FREE_SLOT_NUM_CLR_WIDTH                                   (1U)
#define DPE_VCANCTRL_FREE_SLOT_NUM_CLR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_VCANCTRL_FREE_SLOT_NUM_CLR_SHIFT)) & DPE_VCANCTRL_FREE_SLOT_NUM_CLR_MASK)

/** register DPE_VCAN_TX_SEND_STATUS offset */
#define DPE_VCAN_TX_SEND_STATUS_OFFSET(x, i)                                  (0x30U + (0x4U * (i)) + (0x80U * (x)))

/* DPE_VCAN_TX_SEND_STATUS_PACKET_ID Bit Fields */
#define DPE_VCAN_TX_SEND_STATUS_PACKET_ID_MASK                                (0xFFFFFFU)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_ID_SHIFT                               (0U)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_ID_WIDTH                               (24U)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_ID(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_SEND_STATUS_PACKET_ID_SHIFT)) & DPE_VCAN_TX_SEND_STATUS_PACKET_ID_MASK)

/* DPE_VCAN_TX_SEND_STATUS_DROP_REASON Bit Fields */
#define DPE_VCAN_TX_SEND_STATUS_DROP_REASON_MASK                              (0x7000000U)
#define DPE_VCAN_TX_SEND_STATUS_DROP_REASON_SHIFT                             (24U)
#define DPE_VCAN_TX_SEND_STATUS_DROP_REASON_WIDTH                             (3U)
#define DPE_VCAN_TX_SEND_STATUS_DROP_REASON(x)                                (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_SEND_STATUS_DROP_REASON_SHIFT)) & DPE_VCAN_TX_SEND_STATUS_DROP_REASON_MASK)

/* DPE_VCAN_TX_SEND_STATUS_PACKET_DROP Bit Fields */
#define DPE_VCAN_TX_SEND_STATUS_PACKET_DROP_MASK                              (0x8000000U)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_DROP_SHIFT                             (27U)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_DROP_WIDTH                             (1U)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_DROP(x)                                (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_SEND_STATUS_PACKET_DROP_SHIFT)) & DPE_VCAN_TX_SEND_STATUS_PACKET_DROP_MASK)

/* DPE_VCAN_TX_SEND_STATUS_PACKET_STATUS_VLD Bit Fields */
#define DPE_VCAN_TX_SEND_STATUS_PACKET_STATUS_VLD_MASK                        (0x10000000U)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_STATUS_VLD_SHIFT                       (28U)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_STATUS_VLD_WIDTH                       (1U)
#define DPE_VCAN_TX_SEND_STATUS_PACKET_STATUS_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_SEND_STATUS_PACKET_STATUS_VLD_SHIFT)) & DPE_VCAN_TX_SEND_STATUS_PACKET_STATUS_VLD_MASK)

/* DPE_VCAN_TX_SEND_STATUS0_SEND_TIMEOUT Bit Fields */
#define DPE_VCAN_TX_SEND_STATUS_SEND_TIMEOUT_MASK                             (0x20000000U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_TIMEOUT_SHIFT                            (29U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_TIMEOUT_WIDTH                            (1U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_TIMEOUT(x)                               (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_SEND_STATUS_SEND_TIMEOUT_SHIFT)) & DPE_VCAN_TX_SEND_STATUS_SEND_TIMEOUT_MASK)

/* DPE_VCAN_TX_SEND_STATUS0_SEND_DONE Bit Fields */
#define DPE_VCAN_TX_SEND_STATUS_SEND_DONE_MASK                                (0x40000000U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_DONE_SHIFT                               (30U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_DONE_WIDTH                               (1U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_DONE(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_SEND_STATUS_SEND_DONE_SHIFT)) & DPE_VCAN_TX_SEND_STATUS_SEND_DONE_MASK)

/* DPE_VCAN_TX_SEND_STATUS0_SEND_STATUS_OVERWRITE Bit Fields */
#define DPE_VCAN_TX_SEND_STATUS_SEND_STATUS_OVERWRITE_MASK                    (0x80000000U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_STATUS_OVERWRITE_SHIFT                   (31U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_STATUS_OVERWRITE_WIDTH                   (1U)
#define DPE_VCAN_TX_SEND_STATUS_SEND_STATUS_OVERWRITE(x)                      (((uint32_t)(((uint32_t)(x)) << DPE_VCAN_TX_SEND_STATUS_SEND_STATUS_OVERWRITE_SHIFT)) & DPE_VCAN_TX_SEND_STATUS_SEND_STATUS_OVERWRITE_MASK)

/** register DPE_DIAG_VCAN_RX_PACKET_ADDR offset */
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_OFFSET                                    (0x900U)

/* DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_RX_1ST_PACKET_ADDR Bit Fields */
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_RX_1ST_PACKET_ADDR_MASK              (0xFU)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_RX_1ST_PACKET_ADDR_SHIFT             (0U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_RX_1ST_PACKET_ADDR_WIDTH             (4U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_RX_1ST_PACKET_ADDR(x)                (((uint32_t)(((uint32_t)(x)) << DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_RX_1ST_PACKET_ADDR_SHIFT)) & DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_RX_1ST_PACKET_ADDR_MASK)

/* DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX Bit Fields */
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_MASK            (0xF00U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_SHIFT           (8U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_WIDTH           (4U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX(x)              (((uint32_t)(((uint32_t)(x)) << DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_SHIFT)) & DPE_DIAG_VCAN_RX_PACKET_ADDR_VCAN_NEXT_WR_PACKET_INDEX_MASK)

/* DPE_DIAG_VCAN_RX_PACKET_ADDR_DVCAN_RX_RD_PTR_INDEX Bit Fields */
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_DVCAN_RX_RD_PTR_INDEX_MASK                (0xF0000U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_DVCAN_RX_RD_PTR_INDEX_SHIFT               (16U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_DVCAN_RX_RD_PTR_INDEX_WIDTH               (4U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_DVCAN_RX_RD_PTR_INDEX(x)                  (((uint32_t)(((uint32_t)(x)) << DPE_DIAG_VCAN_RX_PACKET_ADDR_DVCAN_RX_RD_PTR_INDEX_SHIFT)) & DPE_DIAG_VCAN_RX_PACKET_ADDR_DVCAN_RX_RD_PTR_INDEX_MASK)

/* DPE_DIAG_VCAN_RX_PACKET_ADDR_PACKET_POP Bit Fields */
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_PACKET_POP_MASK                           (0x80000000U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_PACKET_POP_SHIFT                          (31U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_PACKET_POP_WIDTH                          (1U)
#define DPE_DIAG_VCAN_RX_PACKET_ADDR_PACKET_POP(x)                             (((uint32_t)(((uint32_t)(x)) << DPE_DIAG_VCAN_RX_PACKET_ADDR_PACKET_POP_SHIFT)) & DPE_DIAG_VCAN_RX_PACKET_ADDR_PACKET_POP_MASK)

/** register DPE_DIAG_VCAN_RX_FIFO_STATUS offset */
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_OFFSET                                    (0x904U)

/* DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_FULL Bit Fields */
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_FULL_MASK                            (0x1U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_FULL_SHIFT                           (0U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_FULL_WIDTH                           (1U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_FULL(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_FULL_SHIFT)) & DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_FULL_MASK)

/* DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_EMPTY Bit Fields */
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_MASK                           (0x2U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_SHIFT                          (1U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_WIDTH                          (1U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_EMPTY(x)                             (((uint32_t)(((uint32_t)(x)) << DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_SHIFT)) & DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_EMPTY_MASK)

/* DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES Bit Fields */
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_MASK                         (0x1F00U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_SHIFT                        (8U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_WIDTH                        (5U)
#define DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES(x)                           (((uint32_t)(((uint32_t)(x)) << DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_SHIFT)) & DPE_DIAG_VCAN_RX_FIFO_STATUS_FIFO_ENTRIES_MASK)

/** register DPE_DIAGVCAN_FIFO_CONFIG offset */
#define DPE_DIAGVCAN_FIFO_CONFIG_OFFSET                                        (0x908U)

/* DPE_DIAGVCAN_FIFO_CONFIG_START_ADDR Bit Fields */
#define DPE_DIAGVCAN_FIFO_CONFIG_START_ADDR_MASK                               (0x1FFFFFFFU)
#define DPE_DIAGVCAN_FIFO_CONFIG_START_ADDR_SHIFT                              (0U)
#define DPE_DIAGVCAN_FIFO_CONFIG_START_ADDR_WIDTH                              (29U)
#define DPE_DIAGVCAN_FIFO_CONFIG_START_ADDR(x)                                 (((uint32_t)(((uint32_t)(x)) << DPE_DIAGVCAN_FIFO_CONFIG_START_ADDR_SHIFT)) & DPE_DIAGVCAN_FIFO_CONFIG_START_ADDR_MASK)

/* DPE_DIAGVCAN_FIFO_CONFIG_EN Bit Fields */
#define DPE_DIAGVCAN_FIFO_CONFIG_EN_MASK                                       (0x80000000U)
#define DPE_DIAGVCAN_FIFO_CONFIG_EN_SHIFT                                      (31U)
#define DPE_DIAGVCAN_FIFO_CONFIG_EN_WIDTH                                      (1U)
#define DPE_DIAGVCAN_FIFO_CONFIG_EN(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_DIAGVCAN_FIFO_CONFIG_EN_SHIFT)) & DPE_DIAGVCAN_FIFO_CONFIG_EN_MASK)

/** register DPE_CONFIG offset */
#define DPE_CONFIG_OFFSET                                                      (0x910U)

/* DPE_CONFIG_CAN_TX_TIMEOUT_CNT Bit Fields */
#define DPE_CONFIG_CAN_TX_TIMEOUT_CNT_MASK                                     (0xFFFFU)
#define DPE_CONFIG_CAN_TX_TIMEOUT_CNT_SHIFT                                    (0U)
#define DPE_CONFIG_CAN_TX_TIMEOUT_CNT_WIDTH                                    (16U)
#define DPE_CONFIG_CAN_TX_TIMEOUT_CNT(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_CAN_TX_TIMEOUT_CNT_SHIFT)) & DPE_CONFIG_CAN_TX_TIMEOUT_CNT_MASK)

/* DPE_CONFIG_DPE_EN Bit Fields */
#define DPE_CONFIG_DPE_EN_MASK                                                 (0x10000U)
#define DPE_CONFIG_DPE_EN_SHIFT                                                (16U)
#define DPE_CONFIG_DPE_EN_WIDTH                                                (1U)
#define DPE_CONFIG_DPE_EN(x)                                                   (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_DPE_EN_SHIFT)) & DPE_CONFIG_DPE_EN_MASK)

/* DPE_CONFIG_SOFT_RST Bit Fields */
#define DPE_CONFIG_SOFT_RST_MASK                                               (0x20000U)
#define DPE_CONFIG_SOFT_RST_SHIFT                                              (17U)
#define DPE_CONFIG_SOFT_RST_WIDTH                                              (1U)
#define DPE_CONFIG_SOFT_RST(x)                                                 (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_SOFT_RST_SHIFT)) & DPE_CONFIG_SOFT_RST_MASK)

/* DPE_CONFIG_FLUSH_ALL Bit Fields */
#define DPE_CONFIG_FLUSH_ALL_MASK                                              (0x40000U)
#define DPE_CONFIG_FLUSH_ALL_SHIFT                                             (18U)
#define DPE_CONFIG_FLUSH_ALL_WIDTH                                             (1U)
#define DPE_CONFIG_FLUSH_ALL(x)                                                (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_FLUSH_ALL_SHIFT)) & DPE_CONFIG_FLUSH_ALL_MASK)

/* DPE_CONFIG_UNRECG_PACKET_DROP Bit Fields */
#define DPE_CONFIG_UNRECG_PACKET_DROP_MASK                                     (0x80000U)
#define DPE_CONFIG_UNRECG_PACKET_DROP_SHIFT                                    (19U)
#define DPE_CONFIG_UNRECG_PACKET_DROP_WIDTH                                    (1U)
#define DPE_CONFIG_UNRECG_PACKET_DROP(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_UNRECG_PACKET_DROP_SHIFT)) & DPE_CONFIG_UNRECG_PACKET_DROP_MASK)

/* DPE_CONFIG_WRONG_DLC_DROP Bit Fields */
#define DPE_CONFIG_WRONG_DLC_DROP_MASK                                         (0x100000U)
#define DPE_CONFIG_WRONG_DLC_DROP_SHIFT                                        (20U)
#define DPE_CONFIG_WRONG_DLC_DROP_WIDTH                                        (1U)
#define DPE_CONFIG_WRONG_DLC_DROP(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_WRONG_DLC_DROP_SHIFT)) & DPE_CONFIG_WRONG_DLC_DROP_MASK)

/* DPE_CONFIG_VCAN_LITTLE_ENDIAN_EN Bit Fields */
#define DPE_CONFIG_VCAN_LITTLE_ENDIAN_EN_MASK                                  (0x200000U)
#define DPE_CONFIG_VCAN_LITTLE_ENDIAN_EN_SHIFT                                 (21U)
#define DPE_CONFIG_VCAN_LITTLE_ENDIAN_EN_WIDTH                                 (1U)
#define DPE_CONFIG_VCAN_LITTLE_ENDIAN_EN(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_VCAN_LITTLE_ENDIAN_EN_SHIFT)) & DPE_CONFIG_VCAN_LITTLE_ENDIAN_EN_MASK)

/* DPE_CONFIG_STATUS Bit Fields */
#define DPE_CONFIG_STATUS_MASK                                                 (0xFF000000U)
#define DPE_CONFIG_STATUS_SHIFT                                                (24U)
#define DPE_CONFIG_STATUS_WIDTH                                                (8U)
#define DPE_CONFIG_STATUS(x)                                                   (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_STATUS_SHIFT)) & DPE_CONFIG_STATUS_MASK)

/** register DPE_ROUTE_TABLE_BASE_ADDR offset */
#define DPE_ROUTE_TABLE_BASE_ADDR_OFFSET                                       (0x918U)

/* DPE_ROUTE_TABLE_BASE_ADDR_BASE_ADDR Bit Fields */
#define DPE_ROUTE_TABLE_BASE_ADDR_BASE_ADDR_MASK                               (0x1FFFFFFFU)
#define DPE_ROUTE_TABLE_BASE_ADDR_BASE_ADDR_SHIFT                              (0U)
#define DPE_ROUTE_TABLE_BASE_ADDR_BASE_ADDR_WIDTH                              (29U)
#define DPE_ROUTE_TABLE_BASE_ADDR_BASE_ADDR(x)                                 (((uint32_t)(((uint32_t)(x)) << DPE_ROUTE_TABLE_BASE_ADDR_BASE_ADDR_SHIFT)) & DPE_ROUTE_TABLE_BASE_ADDR_BASE_ADDR_MASK)

/** register DPE_DMA_CONFIG offset */
#define DPE_DMA_CONFIG_OFFSET                                                  (0x920U)

/* DPE_DMA_CONFIG_CACHE Bit Fields */
#define DPE_DMA_CONFIG_CACHE_MASK                                              (0xFU)
#define DPE_DMA_CONFIG_CACHE_SHIFT                                             (0U)
#define DPE_DMA_CONFIG_CACHE_WIDTH                                             (4U)
#define DPE_DMA_CONFIG_CACHE(x)                                                (((uint32_t)(((uint32_t)(x)) << DPE_DMA_CONFIG_CACHE_SHIFT)) & DPE_DMA_CONFIG_CACHE_MASK)

/* DPE_DMA_CONFIG_PPROT Bit Fields */
#define DPE_DMA_CONFIG_PPROT_MASK                                              (0x70U)
#define DPE_DMA_CONFIG_PPROT_SHIFT                                             (4U)
#define DPE_DMA_CONFIG_PPROT_WIDTH                                             (3U)
#define DPE_DMA_CONFIG_PPROT(x)                                                (((uint32_t)(((uint32_t)(x)) << DPE_DMA_CONFIG_PPROT_SHIFT)) & DPE_DMA_CONFIG_PPROT_MASK)

/* DPE_DMA_CONFIG_HPROT Bit Fields */
#define DPE_DMA_CONFIG_HPROT_MASK                                              (0xF00U)
#define DPE_DMA_CONFIG_HPROT_SHIFT                                             (8U)
#define DPE_DMA_CONFIG_HPROT_WIDTH                                             (4U)
#define DPE_DMA_CONFIG_HPROT(x)                                                (((uint32_t)(((uint32_t)(x)) << DPE_DMA_CONFIG_HPROT_SHIFT)) & DPE_DMA_CONFIG_HPROT_MASK)

/** register DPE_CAN_PACKET_TRACKING_CONFIG offset */
#define DPE_CAN_PACKET_TRACKING_CONFIG_OFFSET                                  (0x924U)

/* DPE_CAN_PACKET_TRACKING_CONFIG_SRC_BUSID Bit Fields */
#define DPE_CAN_PACKET_TRACKING_CONFIG_SRC_BUSID_MASK                          (0x3FU)
#define DPE_CAN_PACKET_TRACKING_CONFIG_SRC_BUSID_SHIFT                         (0U)
#define DPE_CAN_PACKET_TRACKING_CONFIG_SRC_BUSID_WIDTH                         (6U)
#define DPE_CAN_PACKET_TRACKING_CONFIG_SRC_BUSID(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_PACKET_TRACKING_CONFIG_SRC_BUSID_SHIFT)) & DPE_CAN_PACKET_TRACKING_CONFIG_SRC_BUSID_MASK)

/* DPE_CAN_PACKET_TRACKING_CONFIG_LATENCY_VALID Bit Fields */
#define DPE_CAN_PACKET_TRACKING_CONFIG_LATENCY_VALID_MASK                      (0x100U)
#define DPE_CAN_PACKET_TRACKING_CONFIG_LATENCY_VALID_SHIFT                     (8U)
#define DPE_CAN_PACKET_TRACKING_CONFIG_LATENCY_VALID_WIDTH                     (1U)
#define DPE_CAN_PACKET_TRACKING_CONFIG_LATENCY_VALID(x)                        (((uint32_t)(((uint32_t)(x)) << DPE_CAN_PACKET_TRACKING_CONFIG_LATENCY_VALID_SHIFT)) & DPE_CAN_PACKET_TRACKING_CONFIG_LATENCY_VALID_MASK)

/* DPE_CAN_PACKET_TRACKING_CONFIG_PACKET_LATENCY Bit Fields */
#define DPE_CAN_PACKET_TRACKING_CONFIG_PACKET_LATENCY_MASK                     (0xFFFF0000U)
#define DPE_CAN_PACKET_TRACKING_CONFIG_PACKET_LATENCY_SHIFT                    (16U)
#define DPE_CAN_PACKET_TRACKING_CONFIG_PACKET_LATENCY_WIDTH                    (16U)
#define DPE_CAN_PACKET_TRACKING_CONFIG_PACKET_LATENCY(x)                       (((uint32_t)(((uint32_t)(x)) << DPE_CAN_PACKET_TRACKING_CONFIG_PACKET_LATENCY_SHIFT)) & DPE_CAN_PACKET_TRACKING_CONFIG_PACKET_LATENCY_MASK)

/** register DPE_CAN_PACKET_TRACKING_FRAMEID offset */
#define DPE_CAN_PACKET_TRACKING_FRAMEID_OFFSET                                 (0x928U)

/* DPE_CAN_PACKET_TRACKING_FRAMEID_SRC_FRAMEID Bit Fields */
#define DPE_CAN_PACKET_TRACKING_FRAMEID_SRC_FRAMEID_MASK                       (0x1FFFFFFFU)
#define DPE_CAN_PACKET_TRACKING_FRAMEID_SRC_FRAMEID_SHIFT                      (0U)
#define DPE_CAN_PACKET_TRACKING_FRAMEID_SRC_FRAMEID_WIDTH                      (29U)
#define DPE_CAN_PACKET_TRACKING_FRAMEID_SRC_FRAMEID(x)                         (((uint32_t)(((uint32_t)(x)) << DPE_CAN_PACKET_TRACKING_FRAMEID_SRC_FRAMEID_SHIFT)) & DPE_CAN_PACKET_TRACKING_FRAMEID_SRC_FRAMEID_MASK)

/** register DPE_BUS_MIRROR_CONFIG offset */
#define DPE_BUS_MIRROR_CONFIG_OFFSET                                           (0x92CU)

/* DPE_BUS_MIRROR_CONFIG_DST_BUSID Bit Fields */
#define DPE_BUS_MIRROR_CONFIG_DST_BUSID_MASK                                   (0x3FU)
#define DPE_BUS_MIRROR_CONFIG_DST_BUSID_SHIFT                                  (0U)
#define DPE_BUS_MIRROR_CONFIG_DST_BUSID_WIDTH                                  (6U)
#define DPE_BUS_MIRROR_CONFIG_DST_BUSID(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_BUS_MIRROR_CONFIG_DST_BUSID_SHIFT)) & DPE_BUS_MIRROR_CONFIG_DST_BUSID_MASK)

/* DPE_BUS_MIRROR_CONFIG_DST_MB_NUM Bit Fields */
#define DPE_BUS_MIRROR_CONFIG_DST_MB_NUM_MASK                                  (0x700U)
#define DPE_BUS_MIRROR_CONFIG_DST_MB_NUM_SHIFT                                 (8U)
#define DPE_BUS_MIRROR_CONFIG_DST_MB_NUM_WIDTH                                 (3U)
#define DPE_BUS_MIRROR_CONFIG_DST_MB_NUM(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_BUS_MIRROR_CONFIG_DST_MB_NUM_SHIFT)) & DPE_BUS_MIRROR_CONFIG_DST_MB_NUM_MASK)

/** register DPE_TRAFFIC_CTRL offset */
#define DPE_TRAFFIC_CTRL_OFFSET                                                (0x930U)

/* DPE_TRAFFIC_CTRL_EN Bit Fields */
#define DPE_TRAFFIC_CTRL_EN_MASK                                               (0x1U)
#define DPE_TRAFFIC_CTRL_EN_SHIFT                                              (0U)
#define DPE_TRAFFIC_CTRL_EN_WIDTH                                              (1U)
#define DPE_TRAFFIC_CTRL_EN(x)                                                 (((uint32_t)(((uint32_t)(x)) << DPE_TRAFFIC_CTRL_EN_SHIFT)) & DPE_TRAFFIC_CTRL_EN_MASK)

/* DPE_TRAFFIC_CTRL_FORCE_EN Bit Fields */
#define DPE_TRAFFIC_CTRL_FORCE_EN_MASK                                         (0x2U)
#define DPE_TRAFFIC_CTRL_FORCE_EN_SHIFT                                        (1U)
#define DPE_TRAFFIC_CTRL_FORCE_EN_WIDTH                                        (1U)
#define DPE_TRAFFIC_CTRL_FORCE_EN(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_TRAFFIC_CTRL_FORCE_EN_SHIFT)) & DPE_TRAFFIC_CTRL_FORCE_EN_MASK)

/* DPE_TRAFFIC_CTRL_INTERVAL Bit Fields */
#define DPE_TRAFFIC_CTRL_INTERVAL_MASK                                         (0xFFFF0000U)
#define DPE_TRAFFIC_CTRL_INTERVAL_SHIFT                                        (16U)
#define DPE_TRAFFIC_CTRL_INTERVAL_WIDTH                                        (16U)
#define DPE_TRAFFIC_CTRL_INTERVAL(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_TRAFFIC_CTRL_INTERVAL_SHIFT)) & DPE_TRAFFIC_CTRL_INTERVAL_MASK)

/** register DPE_CAN_REQ_MASK offset */
#define DPE_CAN_REQ_MASK_OFFSET(x)                                             (0x940U + (0x4U * (x)))

/* DPE_CAN_REQ_MASK_MASK Bit Fields */
#define DPE_CAN_REQ_MASK_MASK_MASK                                             (0x1U)
#define DPE_CAN_REQ_MASK_MASK_SHIFT                                            (0U)
#define DPE_CAN_REQ_MASK_MASK_WIDTH                                            (1U)
#define DPE_CAN_REQ_MASK_MASK(x)                                               (((uint32_t)(((uint32_t)(x)) << DPE_CAN_REQ_MASK_MASK_SHIFT)) & DPE_CAN_REQ_MASK_MASK_MASK)

/** register DPE_PACKET_FILTER_CONFIG offset */
#define DPE_PACKET_FILTER_CONFIG_OFFSET(x)                                     (0xA00U + (0x10U * (x)))

/* DPE_PACKET_FILTER_CONFIG_FMOD Bit Fields */
#define DPE_PACKET_FILTER_CONFIG_FMOD_MASK                                     (0x3U)
#define DPE_PACKET_FILTER_CONFIG_FMOD_SHIFT                                    (0U)
#define DPE_PACKET_FILTER_CONFIG_FMOD_WIDTH                                    (2U)
#define DPE_PACKET_FILTER_CONFIG_FMOD(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_PACKET_FILTER_CONFIG_FMOD_SHIFT)) & DPE_PACKET_FILTER_CONFIG_FMOD_MASK)

/* DPE_PACKET_FILTER_CONFIG_FTYPE Bit Fields */
#define DPE_PACKET_FILTER_CONFIG_FTYPE_MASK                                    (0x30U)
#define DPE_PACKET_FILTER_CONFIG_FTYPE_SHIFT                                   (4U)
#define DPE_PACKET_FILTER_CONFIG_FTYPE_WIDTH                                   (2U)
#define DPE_PACKET_FILTER_CONFIG_FTYPE(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_PACKET_FILTER_CONFIG_FTYPE_SHIFT)) & DPE_PACKET_FILTER_CONFIG_FTYPE_MASK)

/* DPE_PACKET_FILTER_CONFIG_FSEL Bit Fields */
#define DPE_PACKET_FILTER_CONFIG_FSEL_MASK                                     (0x40U)
#define DPE_PACKET_FILTER_CONFIG_FSEL_SHIFT                                    (6U)
#define DPE_PACKET_FILTER_CONFIG_FSEL_WIDTH                                    (1U)
#define DPE_PACKET_FILTER_CONFIG_FSEL(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_PACKET_FILTER_CONFIG_FSEL_SHIFT)) & DPE_PACKET_FILTER_CONFIG_FSEL_MASK)

/* DPE_PACKET_FILTER_CONFIG_FEN Bit Fields */
#define DPE_PACKET_FILTER_CONFIG_FEN_MASK                                      (0x80U)
#define DPE_PACKET_FILTER_CONFIG_FEN_SHIFT                                     (7U)
#define DPE_PACKET_FILTER_CONFIG_FEN_WIDTH                                     (1U)
#define DPE_PACKET_FILTER_CONFIG_FEN(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_PACKET_FILTER_CONFIG_FEN_SHIFT)) & DPE_PACKET_FILTER_CONFIG_FEN_MASK)

/* DPE_PACKET_FILTER_CONFIG_FBUSID Bit Fields */
#define DPE_PACKET_FILTER_CONFIG_FBUSID_MASK                                   (0x3F00U)
#define DPE_PACKET_FILTER_CONFIG_FBUSID_SHIFT                                  (8U)
#define DPE_PACKET_FILTER_CONFIG_FBUSID_WIDTH                                  (6U)
#define DPE_PACKET_FILTER_CONFIG_FBUSID(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_PACKET_FILTER_CONFIG_FBUSID_SHIFT)) & DPE_PACKET_FILTER_CONFIG_FBUSID_MASK)

/* DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_CLR Bit Fields */
#define DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_CLR_MASK                         (0x8000U)
#define DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_CLR_SHIFT                        (15U)
#define DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_CLR_WIDTH                        (1U)
#define DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_CLR(x)                           (((uint32_t)(((uint32_t)(x)) << DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_CLR_SHIFT)) & DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_CLR_MASK)

/* DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER Bit Fields */
#define DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_MASK                             (0xFFFF0000U)
#define DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_SHIFT                            (16U)
#define DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_WIDTH                            (16U)
#define DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER(x)                               (((uint32_t)(((uint32_t)(x)) << DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_SHIFT)) & DPE_PACKET_FILTER_CONFIG_FLOW_COUNTER_MASK)

/** register DPE_FFID_START offset */
#define DPE_FFID_START_OFFSET(x)                                               (0xA04U + (0x10U * (x)))

/* DPE_FFID_START_FFID_START Bit Fields */
#define DPE_FFID_START_FFID_START_MASK                                         (0x1FFFFFFFU)
#define DPE_FFID_START_FFID_START_SHIFT                                        (0U)
#define DPE_FFID_START_FFID_START_WIDTH                                        (29U)
#define DPE_FFID_START_FFID_START(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_FFID_START_FFID_START_SHIFT)) & DPE_FFID_START_FFID_START_MASK)

/** register DPE_FFID_END offset */
#define DPE_FFID_END_OFFSET(x)                                                 (0xA08U + (0x10U * (x)))

/* DPE_FFID_END_FFID_END Bit Fields */
#define DPE_FFID_END_FFID_END_MASK                                             (0x1FFFFFFFU)
#define DPE_FFID_END_FFID_END_SHIFT                                            (0U)
#define DPE_FFID_END_FFID_END_WIDTH                                            (29U)
#define DPE_FFID_END_FFID_END(x)                                               (((uint32_t)(((uint32_t)(x)) << DPE_FFID_END_FFID_END_SHIFT)) & DPE_FFID_END_FFID_END_MASK)

/** register DPE_PFC_PROT offset */
#define DPE_PFC_PROT_OFFSET(x)                                                 (0xA0CU + (0x10U * (x)))

/* DPE_PFC_PROT_PROT Bit Fields */
#define DPE_PFC_PROT_PROT_MASK                                                 (0x3U)
#define DPE_PFC_PROT_PROT_SHIFT                                                (0U)
#define DPE_PFC_PROT_PROT_WIDTH                                                (2U)
#define DPE_PFC_PROT_PROT(x)                                                   (((uint32_t)(((uint32_t)(x)) << DPE_PFC_PROT_PROT_SHIFT)) & DPE_PFC_PROT_PROT_MASK)

/** register DPE_CAN_TXQUEUE_CONFIG offset */
#define DPE_CAN_TXQUEUE_CONFIG_OFFSET(x)                                       (0x1000U + (0x80U * (x)))

/* DPE_CAN_TXQUEUE_CONFIG_SUB_QUEUE_MB_START_ADDR Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_SUB_QUEUE_MB_START_ADDR_MASK                    (0xFFFU)
#define DPE_CAN_TXQUEUE_CONFIG_SUB_QUEUE_MB_START_ADDR_SHIFT                   (0U)
#define DPE_CAN_TXQUEUE_CONFIG_SUB_QUEUE_MB_START_ADDR_WIDTH                   (12U)
#define DPE_CAN_TXQUEUE_CONFIG_SUB_QUEUE_MB_START_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_SUB_QUEUE_MB_START_ADDR_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_SUB_QUEUE_MB_START_ADDR_MASK)

/* DPE_CAN_TXQUEUE_CONFIG_MB_SEL_CTRL Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_MB_SEL_CTRL_MASK                                (0x1000U)
#define DPE_CAN_TXQUEUE_CONFIG_MB_SEL_CTRL_SHIFT                               (12U)
#define DPE_CAN_TXQUEUE_CONFIG_MB_SEL_CTRL_WIDTH                               (1U)
#define DPE_CAN_TXQUEUE_CONFIG_MB_SEL_CTRL(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_MB_SEL_CTRL_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_MB_SEL_CTRL_MASK)

/* DPE_CAN_TXQUEUE_CONFIG_MB_MODE Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_MB_MODE_MASK                                    (0x2000U)
#define DPE_CAN_TXQUEUE_CONFIG_MB_MODE_SHIFT                                   (13U)
#define DPE_CAN_TXQUEUE_CONFIG_MB_MODE_WIDTH                                   (1U)
#define DPE_CAN_TXQUEUE_CONFIG_MB_MODE(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_MB_MODE_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_MB_MODE_MASK)

/* DPE_CAN_TXQUEUE_CONFIG_PROTOCOL_CONVERT Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_PROTOCOL_CONVERT_MASK                           (0x4000U)
#define DPE_CAN_TXQUEUE_CONFIG_PROTOCOL_CONVERT_SHIFT                          (14U)
#define DPE_CAN_TXQUEUE_CONFIG_PROTOCOL_CONVERT_WIDTH                          (1U)
#define DPE_CAN_TXQUEUE_CONFIG_PROTOCOL_CONVERT(x)                             (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_PROTOCOL_CONVERT_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_PROTOCOL_CONVERT_MASK)

/* DPE_CAN_TXQUEUE_CONFIG_CAN_INTERRUPT_MODE Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_CAN_INTERRUPT_MODE_MASK                         (0x8000U)
#define DPE_CAN_TXQUEUE_CONFIG_CAN_INTERRUPT_MODE_SHIFT                        (15U)
#define DPE_CAN_TXQUEUE_CONFIG_CAN_INTERRUPT_MODE_WIDTH                        (1U)
#define DPE_CAN_TXQUEUE_CONFIG_CAN_INTERRUPT_MODE(x)                           (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_CAN_INTERRUPT_MODE_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_CAN_INTERRUPT_MODE_MASK)

/* DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_MASK                                (0x10000U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_SHIFT                               (16U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_WIDTH                               (1U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_MASK)

/* DPE_CAN_TXQUEUE_CONFIG_QUEUE_SENDING_FLUSH Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_SENDING_FLUSH_MASK                        (0x20000U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_SENDING_FLUSH_SHIFT                       (17U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_SENDING_FLUSH_WIDTH                       (1U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_SENDING_FLUSH(x)                          (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_QUEUE_SENDING_FLUSH_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_QUEUE_SENDING_FLUSH_MASK)

/* DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_DONE Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_DONE_MASK                           (0x40000U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_DONE_SHIFT                          (18U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_DONE_WIDTH                          (1U)
#define DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_DONE(x)                             (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_DONE_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_QUEUE_FLUSH_DONE_MASK)

/* DPE_CAN_TXQUEUE_CONFIG_TIMEOUT_CNT Bit Fields */
#define DPE_CAN_TXQUEUE_CONFIG_TIMEOUT_CNT_MASK                                (0xFF000000U)
#define DPE_CAN_TXQUEUE_CONFIG_TIMEOUT_CNT_SHIFT                               (24U)
#define DPE_CAN_TXQUEUE_CONFIG_TIMEOUT_CNT_WIDTH                               (8U)
#define DPE_CAN_TXQUEUE_CONFIG_TIMEOUT_CNT(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_CAN_TXQUEUE_CONFIG_TIMEOUT_CNT_SHIFT)) & DPE_CAN_TXQUEUE_CONFIG_TIMEOUT_CNT_MASK)

/** register DPE_CAN_PACKET_SEND_STATUS offset */
#define DPE_CAN_PACKET_SEND_STATUS_OFFSET(x)                                   (0x1004U + (0x80U * (x)))

/* DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE Bit Fields */
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_MASK                       (0xFFU)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_SHIFT                      (0U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_WIDTH                      (8U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE(x)                         (((uint32_t)(((uint32_t)(x)) << DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_SHIFT)) & DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_MASK)

/* DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_CLR Bit Fields */
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_CLR_MASK                   (0xFF00U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_CLR_SHIFT                  (8U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_CLR_WIDTH                  (8U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_CLR(x)                     (((uint32_t)(((uint32_t)(x)) << DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_CLR_SHIFT)) & DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_DONE_CLR_MASK)

/* DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT Bit Fields */
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_MASK                    (0xFF0000U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_SHIFT                   (16U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_WIDTH                   (8U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_SHIFT)) & DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_MASK)

/* DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_CLR Bit Fields */
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_CLR_MASK                (0xFF000000U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_CLR_SHIFT               (24U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_CLR_WIDTH               (8U)
#define DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_CLR(x)                  (((uint32_t)(((uint32_t)(x)) << DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_CLR_SHIFT)) & DPE_CAN_PACKET_SEND_STATUS_CAN_MB_SEND_TIMEOUT_CLR_MASK)

/** register DPE_CAN_SUBQUEUE_DROP_STATUS offset */
#define DPE_CAN_SUBQUEUE_DROP_STATUS_OFFSET(x)                                 (0x1008U + (0x80U * (x)))

/* DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS Bit Fields */
#define DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_MASK          (0xFFU)
#define DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_SHIFT         (0U)
#define DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_WIDTH         (8U)
#define DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_SHIFT)) & DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_MASK)

/* DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_CLR Bit Fields */
#define DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_CLR_MASK      (0xFF00U)
#define DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_CLR_SHIFT     (8U)
#define DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_CLR_WIDTH     (8U)
#define DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_CLR(x)        (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_CLR_SHIFT)) & DPE_CAN_SUBQUEUE_DROP_STATUS_SUBQUEUE_PACKET_DROP_STATUS_CLR_MASK)

/** register DPE_CAN_SUBQUEUE_CONFIG offset */
#define DPE_CAN_SUBQUEUE_CONFIG_OFFSET(x)                                      (0x100CU + (0x80U * (x)))

/* DPE_CAN_SUBQUEUE_CONFIG_SQ0_ARBIT_SCHEME Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ0_ARBIT_SCHEME_MASK                          (0x3U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ0_ARBIT_SCHEME_SHIFT                         (0U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ0_ARBIT_SCHEME_WIDTH                         (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ0_ARBIT_SCHEME(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ0_ARBIT_SCHEME_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ0_ARBIT_SCHEME_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ0_REPLACE_EN Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ0_REPLACE_EN_MASK                            (0x4U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ0_REPLACE_EN_SHIFT                           (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ0_REPLACE_EN_WIDTH                           (1U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ0_REPLACE_EN(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ0_REPLACE_EN_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ0_REPLACE_EN_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ1_ARBIT_SCHEME Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ1_ARBIT_SCHEME_MASK                          (0x30U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ1_ARBIT_SCHEME_SHIFT                         (4U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ1_ARBIT_SCHEME_WIDTH                         (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ1_ARBIT_SCHEME(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ1_ARBIT_SCHEME_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ1_ARBIT_SCHEME_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ1_REPLACE_EN Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ1_REPLACE_EN_MASK                            (0x40U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ1_REPLACE_EN_SHIFT                           (6U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ1_REPLACE_EN_WIDTH                           (1U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ1_REPLACE_EN(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ1_REPLACE_EN_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ1_REPLACE_EN_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ2_ARBIT_SCHEME Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ2_ARBIT_SCHEME_MASK                          (0x300U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ2_ARBIT_SCHEME_SHIFT                         (8U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ2_ARBIT_SCHEME_WIDTH                         (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ2_ARBIT_SCHEME(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ2_ARBIT_SCHEME_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ2_ARBIT_SCHEME_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ2_REPLACE_EN Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ2_REPLACE_EN_MASK                            (0x400U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ2_REPLACE_EN_SHIFT                           (10U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ2_REPLACE_EN_WIDTH                           (1U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ2_REPLACE_EN(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ2_REPLACE_EN_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ2_REPLACE_EN_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ3_ARBIT_SCHEME Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ3_ARBIT_SCHEME_MASK                          (0x3000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ3_ARBIT_SCHEME_SHIFT                         (12U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ3_ARBIT_SCHEME_WIDTH                         (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ3_ARBIT_SCHEME(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ3_ARBIT_SCHEME_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ3_ARBIT_SCHEME_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ3_REPLACE_EN Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ3_REPLACE_EN_MASK                            (0x4000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ3_REPLACE_EN_SHIFT                           (14U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ3_REPLACE_EN_WIDTH                           (1U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ3_REPLACE_EN(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ3_REPLACE_EN_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ3_REPLACE_EN_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ4_ARBIT_SCHEME Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ4_ARBIT_SCHEME_MASK                          (0x30000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ4_ARBIT_SCHEME_SHIFT                         (16U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ4_ARBIT_SCHEME_WIDTH                         (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ4_ARBIT_SCHEME(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ4_ARBIT_SCHEME_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ4_ARBIT_SCHEME_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ4_REPLACE_EN Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ4_REPLACE_EN_MASK                            (0x40000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ4_REPLACE_EN_SHIFT                           (18U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ4_REPLACE_EN_WIDTH                           (1U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ4_REPLACE_EN(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ4_REPLACE_EN_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ4_REPLACE_EN_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ5_ARBIT_SCHEME Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ5_ARBIT_SCHEME_MASK                          (0x300000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ5_ARBIT_SCHEME_SHIFT                         (20U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ5_ARBIT_SCHEME_WIDTH                         (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ5_ARBIT_SCHEME(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ5_ARBIT_SCHEME_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ5_ARBIT_SCHEME_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ5_REPLACE_EN Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ5_REPLACE_EN_MASK                            (0x400000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ5_REPLACE_EN_SHIFT                           (22U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ5_REPLACE_EN_WIDTH                           (1U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ5_REPLACE_EN(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ5_REPLACE_EN_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ5_REPLACE_EN_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ6_ARBIT_SCHEME Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ6_ARBIT_SCHEME_MASK                          (0x3000000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ6_ARBIT_SCHEME_SHIFT                         (24U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ6_ARBIT_SCHEME_WIDTH                         (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ6_ARBIT_SCHEME(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ6_ARBIT_SCHEME_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ6_ARBIT_SCHEME_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ6_REPLACE_EN Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ6_REPLACE_EN_MASK                            (0x4000000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ6_REPLACE_EN_SHIFT                           (26U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ6_REPLACE_EN_WIDTH                           (1U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ6_REPLACE_EN(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ6_REPLACE_EN_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ6_REPLACE_EN_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ7_ARBIT_SCHEME Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ7_ARBIT_SCHEME_MASK                          (0x30000000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ7_ARBIT_SCHEME_SHIFT                         (28U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ7_ARBIT_SCHEME_WIDTH                         (2U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ7_ARBIT_SCHEME(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ7_ARBIT_SCHEME_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ7_ARBIT_SCHEME_MASK)

/* DPE_CAN_SUBQUEUE_CONFIG_SQ7_REPLACE_EN Bit Fields */
#define DPE_CAN_SUBQUEUE_CONFIG_SQ7_REPLACE_EN_MASK                            (0x40000000U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ7_REPLACE_EN_SHIFT                           (30U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ7_REPLACE_EN_WIDTH                           (1U)
#define DPE_CAN_SUBQUEUE_CONFIG_SQ7_REPLACE_EN(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_CAN_SUBQUEUE_CONFIG_SQ7_REPLACE_EN_SHIFT)) & DPE_CAN_SUBQUEUE_CONFIG_SQ7_REPLACE_EN_MASK)

/** register DPE_CAN_DROP_STATUS offset */
#define DPE_CAN_DROP_STATUS_OFFSET(x)                                          (0x1010U + (0x80U * (x)))

/* DPE_CAN_DROP_STATUS_CNT Bit Fields */
#define DPE_CAN_DROP_STATUS_CNT_MASK                                           (0xFFU)
#define DPE_CAN_DROP_STATUS_CNT_SHIFT                                          (0U)
#define DPE_CAN_DROP_STATUS_CNT_WIDTH                                          (8U)
#define DPE_CAN_DROP_STATUS_CNT(x)                                             (((uint32_t)(((uint32_t)(x)) << DPE_CAN_DROP_STATUS_CNT_SHIFT)) & DPE_CAN_DROP_STATUS_CNT_MASK)

/* DPE_CAN_DROP_STATUS_CLR Bit Fields */
#define DPE_CAN_DROP_STATUS_CLR_MASK                                           (0x10000U)
#define DPE_CAN_DROP_STATUS_CLR_SHIFT                                          (16U)
#define DPE_CAN_DROP_STATUS_CLR_WIDTH                                          (1U)
#define DPE_CAN_DROP_STATUS_CLR(x)                                             (((uint32_t)(((uint32_t)(x)) << DPE_CAN_DROP_STATUS_CLR_SHIFT)) & DPE_CAN_DROP_STATUS_CLR_MASK)

/** register DPE_CAN_BUFFER_BASE_ADDR offset */
#define DPE_CAN_BUFFER_BASE_ADDR_OFFSET(x)                                     (0x1014U + (0x80U * (x)))

/* DPE_CAN_BUFFER_BASE_ADDR_BASE_ADDR Bit Fields */
#define DPE_CAN_BUFFER_BASE_ADDR_BASE_ADDR_MASK                                (0x1FFFFFFFU)
#define DPE_CAN_BUFFER_BASE_ADDR_BASE_ADDR_SHIFT                               (0U)
#define DPE_CAN_BUFFER_BASE_ADDR_BASE_ADDR_WIDTH                               (29U)
#define DPE_CAN_BUFFER_BASE_ADDR_BASE_ADDR(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_CAN_BUFFER_BASE_ADDR_BASE_ADDR_SHIFT)) & DPE_CAN_BUFFER_BASE_ADDR_BASE_ADDR_MASK)

/** register DPE_CANFD_BASE_ADDR offset */
#define DPE_CANFD_BASE_ADDR_OFFSET(x)                                          (0x2E00U + (0x4U * (x)))

/* DPE_CANFD_BASE_ADDR_BASE_ADDR Bit Fields */
#define DPE_CANFD_BASE_ADDR_BASE_ADDR_MASK                                     (0xFFFFU)
#define DPE_CANFD_BASE_ADDR_BASE_ADDR_SHIFT                                    (0U)
#define DPE_CANFD_BASE_ADDR_BASE_ADDR_WIDTH                                    (16U)
#define DPE_CANFD_BASE_ADDR_BASE_ADDR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_CANFD_BASE_ADDR_BASE_ADDR_SHIFT)) & DPE_CANFD_BASE_ADDR_BASE_ADDR_MASK)

/** register DPE_CANINTEN offset */
#define DPE_CANINTEN_OFFSET                                                    (0x2F00U)

/* DPE_CANINTEN_SEND_DONE_INTEN Bit Fields */
#define DPE_CANINTEN_SEND_DONE_INTEN_MASK                                      (0xFFFFU)
#define DPE_CANINTEN_SEND_DONE_INTEN_SHIFT                                     (0U)
#define DPE_CANINTEN_SEND_DONE_INTEN_WIDTH                                     (16U)
#define DPE_CANINTEN_SEND_DONE_INTEN(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_CANINTEN_SEND_DONE_INTEN_SHIFT)) & DPE_CANINTEN_SEND_DONE_INTEN_MASK)

/* DPE_CANINTEN_MB_TIMEOUT_INTEN Bit Fields */
#define DPE_CANINTEN_MB_TIMEOUT_INTEN_MASK                                     (0xFFFF0000U)
#define DPE_CANINTEN_MB_TIMEOUT_INTEN_SHIFT                                    (16U)
#define DPE_CANINTEN_MB_TIMEOUT_INTEN_WIDTH                                    (16U)
#define DPE_CANINTEN_MB_TIMEOUT_INTEN(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_CANINTEN_MB_TIMEOUT_INTEN_SHIFT)) & DPE_CANINTEN_MB_TIMEOUT_INTEN_MASK)

/** register DPE_CAN_INTSTAT offset */
#define DPE_CAN_INTSTAT_OFFSET                                                 (0x2F04U)

/* DPE_CAN_INTSTAT_SEND_DONE Bit Fields */
#define DPE_CAN_INTSTAT_SEND_DONE_MASK                                         (0xFFFFU)
#define DPE_CAN_INTSTAT_SEND_DONE_SHIFT                                        (0U)
#define DPE_CAN_INTSTAT_SEND_DONE_WIDTH                                        (16U)
#define DPE_CAN_INTSTAT_SEND_DONE(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_CAN_INTSTAT_SEND_DONE_SHIFT)) & DPE_CAN_INTSTAT_SEND_DONE_MASK)

/* DPE_CAN_INTSTAT_MB_TIMEOUT Bit Fields */
#define DPE_CAN_INTSTAT_MB_TIMEOUT_MASK                                        (0xFFFF0000U)
#define DPE_CAN_INTSTAT_MB_TIMEOUT_SHIFT                                       (16U)
#define DPE_CAN_INTSTAT_MB_TIMEOUT_WIDTH                                       (16U)
#define DPE_CAN_INTSTAT_MB_TIMEOUT(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_CAN_INTSTAT_MB_TIMEOUT_SHIFT)) & DPE_CAN_INTSTAT_MB_TIMEOUT_MASK)

/** register DPE_CAN_INTCLR offset */
#define DPE_CAN_INTCLR_OFFSET                                                  (0x2F08U)

/* DPE_CAN_INTCLR_SEND_DONE Bit Fields */
#define DPE_CAN_INTCLR_SEND_DONE_MASK                                          (0xFFFFU)
#define DPE_CAN_INTCLR_SEND_DONE_SHIFT                                         (0U)
#define DPE_CAN_INTCLR_SEND_DONE_WIDTH                                         (16U)
#define DPE_CAN_INTCLR_SEND_DONE(x)                                            (((uint32_t)(((uint32_t)(x)) << DPE_CAN_INTCLR_SEND_DONE_SHIFT)) & DPE_CAN_INTCLR_SEND_DONE_MASK)

/* DPE_CAN_INTCLR_MB_TIMEOUT Bit Fields */
#define DPE_CAN_INTCLR_MB_TIMEOUT_MASK                                         (0xFFFF0000U)
#define DPE_CAN_INTCLR_MB_TIMEOUT_SHIFT                                        (16U)
#define DPE_CAN_INTCLR_MB_TIMEOUT_WIDTH                                        (16U)
#define DPE_CAN_INTCLR_MB_TIMEOUT(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_CAN_INTCLR_MB_TIMEOUT_SHIFT)) & DPE_CAN_INTCLR_MB_TIMEOUT_MASK)

/** register DPE_INTEN offset */
#define DPE_INTEN_OFFSET                                                       (0x2F20U)

/* DPE_INTEN_FLOW_CNT_OVERFLOW Bit Fields */
#define DPE_INTEN_FLOW_CNT_OVERFLOW_MASK                                       (0x1U)
#define DPE_INTEN_FLOW_CNT_OVERFLOW_SHIFT                                      (0U)
#define DPE_INTEN_FLOW_CNT_OVERFLOW_WIDTH                                      (1U)
#define DPE_INTEN_FLOW_CNT_OVERFLOW(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_INTEN_FLOW_CNT_OVERFLOW_SHIFT)) & DPE_INTEN_FLOW_CNT_OVERFLOW_MASK)

/* DPE_INTEN_CAN_PACKET_DROP Bit Fields */
#define DPE_INTEN_CAN_PACKET_DROP_MASK                                         (0x2U)
#define DPE_INTEN_CAN_PACKET_DROP_SHIFT                                        (1U)
#define DPE_INTEN_CAN_PACKET_DROP_WIDTH                                        (1U)
#define DPE_INTEN_CAN_PACKET_DROP(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_INTEN_CAN_PACKET_DROP_SHIFT)) & DPE_INTEN_CAN_PACKET_DROP_MASK)

/* DPE_INTEN_AHB_ERR Bit Fields */
#define DPE_INTEN_AHB_ERR_MASK                                                 (0x100U)
#define DPE_INTEN_AHB_ERR_SHIFT                                                (8U)
#define DPE_INTEN_AHB_ERR_WIDTH                                                (1U)
#define DPE_INTEN_AHB_ERR(x)                                                   (((uint32_t)(((uint32_t)(x)) << DPE_INTEN_AHB_ERR_SHIFT)) & DPE_INTEN_AHB_ERR_MASK)

/* DPE_INTEN_AXI_RD_ERR Bit Fields */
#define DPE_INTEN_AXI_RD_ERR_MASK                                              (0x200U)
#define DPE_INTEN_AXI_RD_ERR_SHIFT                                             (9U)
#define DPE_INTEN_AXI_RD_ERR_WIDTH                                             (1U)
#define DPE_INTEN_AXI_RD_ERR(x)                                                (((uint32_t)(((uint32_t)(x)) << DPE_INTEN_AXI_RD_ERR_SHIFT)) & DPE_INTEN_AXI_RD_ERR_MASK)

/* DPE_INTEN_AXI_BRESP_ERR Bit Fields */
#define DPE_INTEN_AXI_BRESP_ERR_MASK                                           (0x400U)
#define DPE_INTEN_AXI_BRESP_ERR_SHIFT                                          (10U)
#define DPE_INTEN_AXI_BRESP_ERR_WIDTH                                          (1U)
#define DPE_INTEN_AXI_BRESP_ERR(x)                                             (((uint32_t)(((uint32_t)(x)) << DPE_INTEN_AXI_BRESP_ERR_SHIFT)) & DPE_INTEN_AXI_BRESP_ERR_MASK)

/* DPE_INTEN_UNRECOG_PACKET Bit Fields */
#define DPE_INTEN_UNRECOG_PACKET_MASK                                          (0x800U)
#define DPE_INTEN_UNRECOG_PACKET_SHIFT                                         (11U)
#define DPE_INTEN_UNRECOG_PACKET_WIDTH                                         (1U)
#define DPE_INTEN_UNRECOG_PACKET(x)                                            (((uint32_t)(((uint32_t)(x)) << DPE_INTEN_UNRECOG_PACKET_SHIFT)) & DPE_INTEN_UNRECOG_PACKET_MASK)

/** register DPE_INTSTAT offset */
#define DPE_INTSTAT_OFFSET                                                     (0x2F24U)

/* DPE_INTSTAT_FLOW_CNT_OVERFLOW Bit Fields */
#define DPE_INTSTAT_FLOW_CNT_OVERFLOW_MASK                                     (0x1U)
#define DPE_INTSTAT_FLOW_CNT_OVERFLOW_SHIFT                                    (0U)
#define DPE_INTSTAT_FLOW_CNT_OVERFLOW_WIDTH                                    (1U)
#define DPE_INTSTAT_FLOW_CNT_OVERFLOW(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_INTSTAT_FLOW_CNT_OVERFLOW_SHIFT)) & DPE_INTSTAT_FLOW_CNT_OVERFLOW_MASK)

/* DPE_INTSTAT_CAN_PACKET_DROP Bit Fields */
#define DPE_INTSTAT_CAN_PACKET_DROP_MASK                                       (0x2U)
#define DPE_INTSTAT_CAN_PACKET_DROP_SHIFT                                      (1U)
#define DPE_INTSTAT_CAN_PACKET_DROP_WIDTH                                      (1U)
#define DPE_INTSTAT_CAN_PACKET_DROP(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_INTSTAT_CAN_PACKET_DROP_SHIFT)) & DPE_INTSTAT_CAN_PACKET_DROP_MASK)

/* DPE_INTSTAT_AHB_ERR Bit Fields */
#define DPE_INTSTAT_AHB_ERR_MASK                                               (0x100U)
#define DPE_INTSTAT_AHB_ERR_SHIFT                                              (8U)
#define DPE_INTSTAT_AHB_ERR_WIDTH                                              (1U)
#define DPE_INTSTAT_AHB_ERR(x)                                                 (((uint32_t)(((uint32_t)(x)) << DPE_INTSTAT_AHB_ERR_SHIFT)) & DPE_INTSTAT_AHB_ERR_MASK)

/* DPE_INTSTAT_AXI_RD_ERR Bit Fields */
#define DPE_INTSTAT_AXI_RD_ERR_MASK                                            (0x200U)
#define DPE_INTSTAT_AXI_RD_ERR_SHIFT                                           (9U)
#define DPE_INTSTAT_AXI_RD_ERR_WIDTH                                           (1U)
#define DPE_INTSTAT_AXI_RD_ERR(x)                                              (((uint32_t)(((uint32_t)(x)) << DPE_INTSTAT_AXI_RD_ERR_SHIFT)) & DPE_INTSTAT_AXI_RD_ERR_MASK)

/* DPE_INTSTAT_AXI_BRESP_ERR Bit Fields */
#define DPE_INTSTAT_AXI_BRESP_ERR_MASK                                         (0x400U)
#define DPE_INTSTAT_AXI_BRESP_ERR_SHIFT                                        (10U)
#define DPE_INTSTAT_AXI_BRESP_ERR_WIDTH                                        (1U)
#define DPE_INTSTAT_AXI_BRESP_ERR(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_INTSTAT_AXI_BRESP_ERR_SHIFT)) & DPE_INTSTAT_AXI_BRESP_ERR_MASK)

/* DPE_INTSTAT_UNRECOG_PACKET Bit Fields */
#define DPE_INTSTAT_UNRECOG_PACKET_MASK                                        (0x800U)
#define DPE_INTSTAT_UNRECOG_PACKET_SHIFT                                       (11U)
#define DPE_INTSTAT_UNRECOG_PACKET_WIDTH                                       (1U)
#define DPE_INTSTAT_UNRECOG_PACKET(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_INTSTAT_UNRECOG_PACKET_SHIFT)) & DPE_INTSTAT_UNRECOG_PACKET_MASK)

/** register DPE_INTCLR offset */
#define DPE_INTCLR_OFFSET                                                      (0x2F28U)

/* DPE_INTCLR_FLOW_CNT_OVERFLOW Bit Fields */
#define DPE_INTCLR_FLOW_CNT_OVERFLOW_MASK                                      (0x1U)
#define DPE_INTCLR_FLOW_CNT_OVERFLOW_SHIFT                                     (0U)
#define DPE_INTCLR_FLOW_CNT_OVERFLOW_WIDTH                                     (1U)
#define DPE_INTCLR_FLOW_CNT_OVERFLOW(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_INTCLR_FLOW_CNT_OVERFLOW_SHIFT)) & DPE_INTCLR_FLOW_CNT_OVERFLOW_MASK)

/* DPE_INTCLR_CAN_PACKET_DROP Bit Fields */
#define DPE_INTCLR_CAN_PACKET_DROP_MASK                                        (0x2U)
#define DPE_INTCLR_CAN_PACKET_DROP_SHIFT                                       (1U)
#define DPE_INTCLR_CAN_PACKET_DROP_WIDTH                                       (1U)
#define DPE_INTCLR_CAN_PACKET_DROP(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_INTCLR_CAN_PACKET_DROP_SHIFT)) & DPE_INTCLR_CAN_PACKET_DROP_MASK)

/* DPE_INTCLR_AHB_ERR Bit Fields */
#define DPE_INTCLR_AHB_ERR_MASK                                                (0x100U)
#define DPE_INTCLR_AHB_ERR_SHIFT                                               (8U)
#define DPE_INTCLR_AHB_ERR_WIDTH                                               (1U)
#define DPE_INTCLR_AHB_ERR(x)                                                  (((uint32_t)(((uint32_t)(x)) << DPE_INTCLR_AHB_ERR_SHIFT)) & DPE_INTCLR_AHB_ERR_MASK)

/* DPE_INTCLR_AXI_RD_ERR Bit Fields */
#define DPE_INTCLR_AXI_RD_ERR_MASK                                             (0x200U)
#define DPE_INTCLR_AXI_RD_ERR_SHIFT                                            (9U)
#define DPE_INTCLR_AXI_RD_ERR_WIDTH                                            (1U)
#define DPE_INTCLR_AXI_RD_ERR(x)                                               (((uint32_t)(((uint32_t)(x)) << DPE_INTCLR_AXI_RD_ERR_SHIFT)) & DPE_INTCLR_AXI_RD_ERR_MASK)

/* DPE_INTCLR_AXI_BRESP_ERR Bit Fields */
#define DPE_INTCLR_AXI_BRESP_ERR_MASK                                          (0x400U)
#define DPE_INTCLR_AXI_BRESP_ERR_SHIFT                                         (10U)
#define DPE_INTCLR_AXI_BRESP_ERR_WIDTH                                         (1U)
#define DPE_INTCLR_AXI_BRESP_ERR(x)                                            (((uint32_t)(((uint32_t)(x)) << DPE_INTCLR_AXI_BRESP_ERR_SHIFT)) & DPE_INTCLR_AXI_BRESP_ERR_MASK)

/* DPE_INTCLR_UNRECOG_PACKET Bit Fields */
#define DPE_INTCLR_UNRECOG_PACKET_MASK                                         (0x800U)
#define DPE_INTCLR_UNRECOG_PACKET_SHIFT                                        (11U)
#define DPE_INTCLR_UNRECOG_PACKET_WIDTH                                        (1U)
#define DPE_INTCLR_UNRECOG_PACKET(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_INTCLR_UNRECOG_PACKET_SHIFT)) & DPE_INTCLR_UNRECOG_PACKET_MASK)

/** register DPE_FUSA_INTEN offset */
#define DPE_FUSA_INTEN_OFFSET                                                  (0x2F30U)

/* DPE_FUSA_INTEN_RTI_MEM_ECC_ERR Bit Fields */
#define DPE_FUSA_INTEN_RTI_MEM_ECC_ERR_MASK                                    (0x1U)
#define DPE_FUSA_INTEN_RTI_MEM_ECC_ERR_SHIFT                                   (0U)
#define DPE_FUSA_INTEN_RTI_MEM_ECC_ERR_WIDTH                                   (1U)
#define DPE_FUSA_INTEN_RTI_MEM_ECC_ERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RTI_MEM_ECC_ERR_SHIFT)) & DPE_FUSA_INTEN_RTI_MEM_ECC_ERR_MASK)

/* DPE_FUSA_INTEN_IN_SIG_ERR Bit Fields */
#define DPE_FUSA_INTEN_IN_SIG_ERR_MASK                                         (0x2U)
#define DPE_FUSA_INTEN_IN_SIG_ERR_SHIFT                                        (1U)
#define DPE_FUSA_INTEN_IN_SIG_ERR_WIDTH                                        (1U)
#define DPE_FUSA_INTEN_IN_SIG_ERR(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_IN_SIG_ERR_SHIFT)) & DPE_FUSA_INTEN_IN_SIG_ERR_MASK)

/* DPE_FUSA_INTEN_ARREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_ARREADY_UNCERR_MASK                                     (0x4U)
#define DPE_FUSA_INTEN_ARREADY_UNCERR_SHIFT                                    (2U)
#define DPE_FUSA_INTEN_ARREADY_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTEN_ARREADY_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_ARREADY_UNCERR_SHIFT)) & DPE_FUSA_INTEN_ARREADY_UNCERR_MASK)

/* DPE_FUSA_INTEN_BCTL_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_BCTL_UNCERR_MASK                                        (0x8U)
#define DPE_FUSA_INTEN_BCTL_UNCERR_SHIFT                                       (3U)
#define DPE_FUSA_INTEN_BCTL_UNCERR_WIDTH                                       (1U)
#define DPE_FUSA_INTEN_BCTL_UNCERR(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_BCTL_UNCERR_SHIFT)) & DPE_FUSA_INTEN_BCTL_UNCERR_MASK)

/* DPE_FUSA_INTEN_BID_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_BID_UNCERR_MASK                                         (0x10U)
#define DPE_FUSA_INTEN_BID_UNCERR_SHIFT                                        (4U)
#define DPE_FUSA_INTEN_BID_UNCERR_WIDTH                                        (1U)
#define DPE_FUSA_INTEN_BID_UNCERR(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_BID_UNCERR_SHIFT)) & DPE_FUSA_INTEN_BID_UNCERR_MASK)

/* DPE_FUSA_INTEN_BVALID_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_BVALID_UNCERR_MASK                                      (0x20U)
#define DPE_FUSA_INTEN_BVALID_UNCERR_SHIFT                                     (5U)
#define DPE_FUSA_INTEN_BVALID_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_BVALID_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_BVALID_UNCERR_SHIFT)) & DPE_FUSA_INTEN_BVALID_UNCERR_MASK)

/* DPE_FUSA_INTEN_HRDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_HRDATA_UNCERR_MASK                                      (0x40U)
#define DPE_FUSA_INTEN_HRDATA_UNCERR_SHIFT                                     (6U)
#define DPE_FUSA_INTEN_HRDATA_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_HRDATA_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_HRDATA_UNCERR_SHIFT)) & DPE_FUSA_INTEN_HRDATA_UNCERR_MASK)

/* DPE_FUSA_INTEN_HRDATA_FATAL Bit Fields */
#define DPE_FUSA_INTEN_HRDATA_FATAL_MASK                                       (0x80U)
#define DPE_FUSA_INTEN_HRDATA_FATAL_SHIFT                                      (7U)
#define DPE_FUSA_INTEN_HRDATA_FATAL_WIDTH                                      (1U)
#define DPE_FUSA_INTEN_HRDATA_FATAL(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_HRDATA_FATAL_SHIFT)) & DPE_FUSA_INTEN_HRDATA_FATAL_MASK)

/* DPE_FUSA_INTEN_HRESP_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_HRESP_UNCERR_MASK                                       (0x100U)
#define DPE_FUSA_INTEN_HRESP_UNCERR_SHIFT                                      (8U)
#define DPE_FUSA_INTEN_HRESP_UNCERR_WIDTH                                      (1U)
#define DPE_FUSA_INTEN_HRESP_UNCERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_HRESP_UNCERR_SHIFT)) & DPE_FUSA_INTEN_HRESP_UNCERR_MASK)

/* DPE_FUSA_INTEN_PADDR_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_PADDR_UNCERR_MASK                                       (0x200U)
#define DPE_FUSA_INTEN_PADDR_UNCERR_SHIFT                                      (9U)
#define DPE_FUSA_INTEN_PADDR_UNCERR_WIDTH                                      (1U)
#define DPE_FUSA_INTEN_PADDR_UNCERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_PADDR_UNCERR_SHIFT)) & DPE_FUSA_INTEN_PADDR_UNCERR_MASK)

/* DPE_FUSA_INTEN_PCTRL0_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_PCTRL0_UNCERR_MASK                                      (0x400U)
#define DPE_FUSA_INTEN_PCTRL0_UNCERR_SHIFT                                     (10U)
#define DPE_FUSA_INTEN_PCTRL0_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_PCTRL0_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_PCTRL0_UNCERR_SHIFT)) & DPE_FUSA_INTEN_PCTRL0_UNCERR_MASK)

/* DPE_FUSA_INTEN_PCTRL1_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_PCTRL1_UNCERR_MASK                                      (0x800U)
#define DPE_FUSA_INTEN_PCTRL1_UNCERR_SHIFT                                     (11U)
#define DPE_FUSA_INTEN_PCTRL1_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_PCTRL1_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_PCTRL1_UNCERR_SHIFT)) & DPE_FUSA_INTEN_PCTRL1_UNCERR_MASK)

/* DPE_FUSA_INTEN_PWDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_PWDATA_UNCERR_MASK                                      (0x1000U)
#define DPE_FUSA_INTEN_PWDATA_UNCERR_SHIFT                                     (12U)
#define DPE_FUSA_INTEN_PWDATA_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_PWDATA_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_PWDATA_UNCERR_SHIFT)) & DPE_FUSA_INTEN_PWDATA_UNCERR_MASK)

/* DPE_FUSA_INTEN_PWDATA_FATAL Bit Fields */
#define DPE_FUSA_INTEN_PWDATA_FATAL_MASK                                       (0x2000U)
#define DPE_FUSA_INTEN_PWDATA_FATAL_SHIFT                                      (13U)
#define DPE_FUSA_INTEN_PWDATA_FATAL_WIDTH                                      (1U)
#define DPE_FUSA_INTEN_PWDATA_FATAL(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_PWDATA_FATAL_SHIFT)) & DPE_FUSA_INTEN_PWDATA_FATAL_MASK)

/* DPE_FUSA_INTEN_RCTL_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_RCTL_UNCERR_MASK                                        (0x4000U)
#define DPE_FUSA_INTEN_RCTL_UNCERR_SHIFT                                       (14U)
#define DPE_FUSA_INTEN_RCTL_UNCERR_WIDTH                                       (1U)
#define DPE_FUSA_INTEN_RCTL_UNCERR(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RCTL_UNCERR_SHIFT)) & DPE_FUSA_INTEN_RCTL_UNCERR_MASK)

/* DPE_FUSA_INTEN_RID_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_RID_UNCERR_MASK                                         (0x8000U)
#define DPE_FUSA_INTEN_RID_UNCERR_SHIFT                                        (15U)
#define DPE_FUSA_INTEN_RID_UNCERR_WIDTH                                        (1U)
#define DPE_FUSA_INTEN_RID_UNCERR(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RID_UNCERR_SHIFT)) & DPE_FUSA_INTEN_RID_UNCERR_MASK)

/* DPE_FUSA_INTEN_RDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_RDATA_UNCERR_MASK                                       (0x10000U)
#define DPE_FUSA_INTEN_RDATA_UNCERR_SHIFT                                      (16U)
#define DPE_FUSA_INTEN_RDATA_UNCERR_WIDTH                                      (1U)
#define DPE_FUSA_INTEN_RDATA_UNCERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RDATA_UNCERR_SHIFT)) & DPE_FUSA_INTEN_RDATA_UNCERR_MASK)

/* DPE_FUSA_INTEN_RVALID_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_RVALID_UNCERR_MASK                                      (0x20000U)
#define DPE_FUSA_INTEN_RVALID_UNCERR_SHIFT                                     (17U)
#define DPE_FUSA_INTEN_RVALID_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_RVALID_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RVALID_UNCERR_SHIFT)) & DPE_FUSA_INTEN_RVALID_UNCERR_MASK)

/* DPE_FUSA_INTEN_RDATA_FATAL Bit Fields */
#define DPE_FUSA_INTEN_RDATA_FATAL_MASK                                        (0x40000U)
#define DPE_FUSA_INTEN_RDATA_FATAL_SHIFT                                       (18U)
#define DPE_FUSA_INTEN_RDATA_FATAL_WIDTH                                       (1U)
#define DPE_FUSA_INTEN_RDATA_FATAL(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RDATA_FATAL_SHIFT)) & DPE_FUSA_INTEN_RDATA_FATAL_MASK)

/* DPE_FUSA_INTEN_WREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_WREADY_UNCERR_MASK                                      (0x80000U)
#define DPE_FUSA_INTEN_WREADY_UNCERR_SHIFT                                     (19U)
#define DPE_FUSA_INTEN_WREADY_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_WREADY_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_WREADY_UNCERR_SHIFT)) & DPE_FUSA_INTEN_WREADY_UNCERR_MASK)

/* DPE_FUSA_INTEN_REOBI_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_REOBI_UNCERR_MASK                                       (0x100000U)
#define DPE_FUSA_INTEN_REOBI_UNCERR_SHIFT                                      (20U)
#define DPE_FUSA_INTEN_REOBI_UNCERR_WIDTH                                      (1U)
#define DPE_FUSA_INTEN_REOBI_UNCERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_REOBI_UNCERR_SHIFT)) & DPE_FUSA_INTEN_REOBI_UNCERR_MASK)

/* DPE_FUSA_INTEN_HRDATA_CORERR Bit Fields */
#define DPE_FUSA_INTEN_HRDATA_CORERR_MASK                                      (0x200000U)
#define DPE_FUSA_INTEN_HRDATA_CORERR_SHIFT                                     (21U)
#define DPE_FUSA_INTEN_HRDATA_CORERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_HRDATA_CORERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_HRDATA_CORERR_SHIFT)) & DPE_FUSA_INTEN_HRDATA_CORERR_MASK)

/* DPE_FUSA_INTEN_PWDATA_CORERR Bit Fields */
#define DPE_FUSA_INTEN_PWDATA_CORERR_MASK                                      (0x400000U)
#define DPE_FUSA_INTEN_PWDATA_CORERR_SHIFT                                     (22U)
#define DPE_FUSA_INTEN_PWDATA_CORERR_WIDTH                                     (1U)
#define DPE_FUSA_INTEN_PWDATA_CORERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_PWDATA_CORERR_SHIFT)) & DPE_FUSA_INTEN_PWDATA_CORERR_MASK)

/* DPE_FUSA_INTEN_RDATA_CORERR Bit Fields */
#define DPE_FUSA_INTEN_RDATA_CORERR_MASK                                       (0x800000U)
#define DPE_FUSA_INTEN_RDATA_CORERR_SHIFT                                      (23U)
#define DPE_FUSA_INTEN_RDATA_CORERR_WIDTH                                      (1U)
#define DPE_FUSA_INTEN_RDATA_CORERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RDATA_CORERR_SHIFT)) & DPE_FUSA_INTEN_RDATA_CORERR_MASK)

/* DPE_FUSA_INTEN_RTI_MEM_CORERR Bit Fields */
#define DPE_FUSA_INTEN_RTI_MEM_CORERR_MASK                                     (0x1000000U)
#define DPE_FUSA_INTEN_RTI_MEM_CORERR_SHIFT                                    (24U)
#define DPE_FUSA_INTEN_RTI_MEM_CORERR_WIDTH                                    (1U)
#define DPE_FUSA_INTEN_RTI_MEM_CORERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RTI_MEM_CORERR_SHIFT)) & DPE_FUSA_INTEN_RTI_MEM_CORERR_MASK)

/* DPE_FUSA_INTEN_AWREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_AWREADY_UNCERR_MASK                                     (0x2000000U)
#define DPE_FUSA_INTEN_AWREADY_UNCERR_SHIFT                                    (25U)
#define DPE_FUSA_INTEN_AWREADY_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTEN_AWREADY_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_AWREADY_UNCERR_SHIFT)) & DPE_FUSA_INTEN_AWREADY_UNCERR_MASK)

/* DPE_FUSA_INTEN_LOCKSTEP_ERR Bit Fields */
#define DPE_FUSA_INTEN_LOCKSTEP_ERR_MASK                                       (0x4000000U)
#define DPE_FUSA_INTEN_LOCKSTEP_ERR_SHIFT                                      (26U)
#define DPE_FUSA_INTEN_LOCKSTEP_ERR_WIDTH                                      (1U)
#define DPE_FUSA_INTEN_LOCKSTEP_ERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_LOCKSTEP_ERR_SHIFT)) & DPE_FUSA_INTEN_LOCKSTEP_ERR_MASK)

/* DPE_FUSA_INTEN_RTC_FIFO_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_RTC_FIFO_UNCERR_MASK                                    (0x8000000U)
#define DPE_FUSA_INTEN_RTC_FIFO_UNCERR_SHIFT                                   (27U)
#define DPE_FUSA_INTEN_RTC_FIFO_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTEN_RTC_FIFO_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RTC_FIFO_UNCERR_SHIFT)) & DPE_FUSA_INTEN_RTC_FIFO_UNCERR_MASK)

/* DPE_FUSA_INTEN_RTC_FIFO_CORERR Bit Fields */
#define DPE_FUSA_INTEN_RTC_FIFO_CORERR_MASK                                    (0x10000000U)
#define DPE_FUSA_INTEN_RTC_FIFO_CORERR_SHIFT                                   (28U)
#define DPE_FUSA_INTEN_RTC_FIFO_CORERR_WIDTH                                   (1U)
#define DPE_FUSA_INTEN_RTC_FIFO_CORERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_RTC_FIFO_CORERR_SHIFT)) & DPE_FUSA_INTEN_RTC_FIFO_CORERR_MASK)

/* DPE_FUSA_INTEN_QUEUE_FIFO_UNCERR Bit Fields */
#define DPE_FUSA_INTEN_QUEUE_FIFO_UNCERR_MASK                                  (0x20000000U)
#define DPE_FUSA_INTEN_QUEUE_FIFO_UNCERR_SHIFT                                 (29U)
#define DPE_FUSA_INTEN_QUEUE_FIFO_UNCERR_WIDTH                                 (1U)
#define DPE_FUSA_INTEN_QUEUE_FIFO_UNCERR(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_QUEUE_FIFO_UNCERR_SHIFT)) & DPE_FUSA_INTEN_QUEUE_FIFO_UNCERR_MASK)

/* DPE_FUSA_INTEN_QUEUE_FIFO_CORERR Bit Fields */
#define DPE_FUSA_INTEN_QUEUE_FIFO_CORERR_MASK                                  (0x40000000U)
#define DPE_FUSA_INTEN_QUEUE_FIFO_CORERR_SHIFT                                 (30U)
#define DPE_FUSA_INTEN_QUEUE_FIFO_CORERR_WIDTH                                 (1U)
#define DPE_FUSA_INTEN_QUEUE_FIFO_CORERR(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_QUEUE_FIFO_CORERR_SHIFT)) & DPE_FUSA_INTEN_QUEUE_FIFO_CORERR_MASK)

/* DPE_FUSA_INTEN_PACKET_CRC_ERR Bit Fields */
#define DPE_FUSA_INTEN_PACKET_CRC_ERR_MASK                                     (0x80000000U)
#define DPE_FUSA_INTEN_PACKET_CRC_ERR_SHIFT                                    (31U)
#define DPE_FUSA_INTEN_PACKET_CRC_ERR_WIDTH                                    (1U)
#define DPE_FUSA_INTEN_PACKET_CRC_ERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTEN_PACKET_CRC_ERR_SHIFT)) & DPE_FUSA_INTEN_PACKET_CRC_ERR_MASK)

/** register DPE_FUSA_INTSTAT offset */
#define DPE_FUSA_INTSTAT_OFFSET                                                (0x2F34U)

/* DPE_FUSA_INTSTAT_RTI_MEM_ECC_ERR Bit Fields */
#define DPE_FUSA_INTSTAT_RTI_MEM_ECC_ERR_MASK                                  (0x1U)
#define DPE_FUSA_INTSTAT_RTI_MEM_ECC_ERR_SHIFT                                 (0U)
#define DPE_FUSA_INTSTAT_RTI_MEM_ECC_ERR_WIDTH                                 (1U)
#define DPE_FUSA_INTSTAT_RTI_MEM_ECC_ERR(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RTI_MEM_ECC_ERR_SHIFT)) & DPE_FUSA_INTSTAT_RTI_MEM_ECC_ERR_MASK)

/* DPE_FUSA_INTSTAT_IN_SIG_ERR Bit Fields */
#define DPE_FUSA_INTSTAT_IN_SIG_ERR_MASK                                       (0x2U)
#define DPE_FUSA_INTSTAT_IN_SIG_ERR_SHIFT                                      (1U)
#define DPE_FUSA_INTSTAT_IN_SIG_ERR_WIDTH                                      (1U)
#define DPE_FUSA_INTSTAT_IN_SIG_ERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_IN_SIG_ERR_SHIFT)) & DPE_FUSA_INTSTAT_IN_SIG_ERR_MASK)

/* DPE_FUSA_INTSTAT_ARREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_ARREADY_UNCERR_MASK                                   (0x4U)
#define DPE_FUSA_INTSTAT_ARREADY_UNCERR_SHIFT                                  (2U)
#define DPE_FUSA_INTSTAT_ARREADY_UNCERR_WIDTH                                  (1U)
#define DPE_FUSA_INTSTAT_ARREADY_UNCERR(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_ARREADY_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_ARREADY_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_BCTL_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_BCTL_UNCERR_MASK                                      (0x8U)
#define DPE_FUSA_INTSTAT_BCTL_UNCERR_SHIFT                                     (3U)
#define DPE_FUSA_INTSTAT_BCTL_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTSTAT_BCTL_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_BCTL_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_BCTL_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_BID_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_BID_UNCERR_MASK                                       (0x10U)
#define DPE_FUSA_INTSTAT_BID_UNCERR_SHIFT                                      (4U)
#define DPE_FUSA_INTSTAT_BID_UNCERR_WIDTH                                      (1U)
#define DPE_FUSA_INTSTAT_BID_UNCERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_BID_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_BID_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_BVALID_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_BVALID_UNCERR_MASK                                    (0x20U)
#define DPE_FUSA_INTSTAT_BVALID_UNCERR_SHIFT                                   (5U)
#define DPE_FUSA_INTSTAT_BVALID_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_BVALID_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_BVALID_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_BVALID_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_HRDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_HRDATA_UNCERR_MASK                                    (0x40U)
#define DPE_FUSA_INTSTAT_HRDATA_UNCERR_SHIFT                                   (6U)
#define DPE_FUSA_INTSTAT_HRDATA_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_HRDATA_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_HRDATA_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_HRDATA_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_HRDATA_FATAL Bit Fields */
#define DPE_FUSA_INTSTAT_HRDATA_FATAL_MASK                                     (0x80U)
#define DPE_FUSA_INTSTAT_HRDATA_FATAL_SHIFT                                    (7U)
#define DPE_FUSA_INTSTAT_HRDATA_FATAL_WIDTH                                    (1U)
#define DPE_FUSA_INTSTAT_HRDATA_FATAL(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_HRDATA_FATAL_SHIFT)) & DPE_FUSA_INTSTAT_HRDATA_FATAL_MASK)

/* DPE_FUSA_INTSTAT_HRESP_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_HRESP_UNCERR_MASK                                     (0x100U)
#define DPE_FUSA_INTSTAT_HRESP_UNCERR_SHIFT                                    (8U)
#define DPE_FUSA_INTSTAT_HRESP_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTSTAT_HRESP_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_HRESP_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_HRESP_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_PADDR_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_PADDR_UNCERR_MASK                                     (0x200U)
#define DPE_FUSA_INTSTAT_PADDR_UNCERR_SHIFT                                    (9U)
#define DPE_FUSA_INTSTAT_PADDR_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTSTAT_PADDR_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_PADDR_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_PADDR_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_PCTRL0_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_PCTRL0_UNCERR_MASK                                    (0x400U)
#define DPE_FUSA_INTSTAT_PCTRL0_UNCERR_SHIFT                                   (10U)
#define DPE_FUSA_INTSTAT_PCTRL0_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_PCTRL0_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_PCTRL0_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_PCTRL0_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_PCTRL1_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_PCTRL1_UNCERR_MASK                                    (0x800U)
#define DPE_FUSA_INTSTAT_PCTRL1_UNCERR_SHIFT                                   (11U)
#define DPE_FUSA_INTSTAT_PCTRL1_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_PCTRL1_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_PCTRL1_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_PCTRL1_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_PWDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_PWDATA_UNCERR_MASK                                    (0x1000U)
#define DPE_FUSA_INTSTAT_PWDATA_UNCERR_SHIFT                                   (12U)
#define DPE_FUSA_INTSTAT_PWDATA_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_PWDATA_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_PWDATA_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_PWDATA_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_PWDATA_FATAL Bit Fields */
#define DPE_FUSA_INTSTAT_PWDATA_FATAL_MASK                                     (0x2000U)
#define DPE_FUSA_INTSTAT_PWDATA_FATAL_SHIFT                                    (13U)
#define DPE_FUSA_INTSTAT_PWDATA_FATAL_WIDTH                                    (1U)
#define DPE_FUSA_INTSTAT_PWDATA_FATAL(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_PWDATA_FATAL_SHIFT)) & DPE_FUSA_INTSTAT_PWDATA_FATAL_MASK)

/* DPE_FUSA_INTSTAT_RCTL_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_RCTL_UNCERR_MASK                                      (0x4000U)
#define DPE_FUSA_INTSTAT_RCTL_UNCERR_SHIFT                                     (14U)
#define DPE_FUSA_INTSTAT_RCTL_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTSTAT_RCTL_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RCTL_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_RCTL_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_RID_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_RID_UNCERR_MASK                                       (0x8000U)
#define DPE_FUSA_INTSTAT_RID_UNCERR_SHIFT                                      (15U)
#define DPE_FUSA_INTSTAT_RID_UNCERR_WIDTH                                      (1U)
#define DPE_FUSA_INTSTAT_RID_UNCERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RID_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_RID_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_RDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_RDATA_UNCERR_MASK                                     (0x10000U)
#define DPE_FUSA_INTSTAT_RDATA_UNCERR_SHIFT                                    (16U)
#define DPE_FUSA_INTSTAT_RDATA_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTSTAT_RDATA_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RDATA_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_RDATA_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_RVALID_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_RVALID_UNCERR_MASK                                    (0x20000U)
#define DPE_FUSA_INTSTAT_RVALID_UNCERR_SHIFT                                   (17U)
#define DPE_FUSA_INTSTAT_RVALID_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_RVALID_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RVALID_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_RVALID_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_RDATA_FATAL Bit Fields */
#define DPE_FUSA_INTSTAT_RDATA_FATAL_MASK                                      (0x40000U)
#define DPE_FUSA_INTSTAT_RDATA_FATAL_SHIFT                                     (18U)
#define DPE_FUSA_INTSTAT_RDATA_FATAL_WIDTH                                     (1U)
#define DPE_FUSA_INTSTAT_RDATA_FATAL(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RDATA_FATAL_SHIFT)) & DPE_FUSA_INTSTAT_RDATA_FATAL_MASK)

/* DPE_FUSA_INTSTAT_WREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_WREADY_UNCERR_MASK                                    (0x80000U)
#define DPE_FUSA_INTSTAT_WREADY_UNCERR_SHIFT                                   (19U)
#define DPE_FUSA_INTSTAT_WREADY_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_WREADY_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_WREADY_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_WREADY_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_REOBI_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_REOBI_UNCERR_MASK                                     (0x100000U)
#define DPE_FUSA_INTSTAT_REOBI_UNCERR_SHIFT                                    (20U)
#define DPE_FUSA_INTSTAT_REOBI_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTSTAT_REOBI_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_REOBI_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_REOBI_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_HRDATA_CORERR Bit Fields */
#define DPE_FUSA_INTSTAT_HRDATA_CORERR_MASK                                    (0x200000U)
#define DPE_FUSA_INTSTAT_HRDATA_CORERR_SHIFT                                   (21U)
#define DPE_FUSA_INTSTAT_HRDATA_CORERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_HRDATA_CORERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_HRDATA_CORERR_SHIFT)) & DPE_FUSA_INTSTAT_HRDATA_CORERR_MASK)

/* DPE_FUSA_INTSTAT_PWDATA_CORERR Bit Fields */
#define DPE_FUSA_INTSTAT_PWDATA_CORERR_MASK                                    (0x400000U)
#define DPE_FUSA_INTSTAT_PWDATA_CORERR_SHIFT                                   (22U)
#define DPE_FUSA_INTSTAT_PWDATA_CORERR_WIDTH                                   (1U)
#define DPE_FUSA_INTSTAT_PWDATA_CORERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_PWDATA_CORERR_SHIFT)) & DPE_FUSA_INTSTAT_PWDATA_CORERR_MASK)

/* DPE_FUSA_INTSTAT_RDATA_CORERR Bit Fields */
#define DPE_FUSA_INTSTAT_RDATA_CORERR_MASK                                     (0x800000U)
#define DPE_FUSA_INTSTAT_RDATA_CORERR_SHIFT                                    (23U)
#define DPE_FUSA_INTSTAT_RDATA_CORERR_WIDTH                                    (1U)
#define DPE_FUSA_INTSTAT_RDATA_CORERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RDATA_CORERR_SHIFT)) & DPE_FUSA_INTSTAT_RDATA_CORERR_MASK)

/* DPE_FUSA_INTSTAT_RTI_MEM_CORERR Bit Fields */
#define DPE_FUSA_INTSTAT_RTI_MEM_CORERR_MASK                                   (0x1000000U)
#define DPE_FUSA_INTSTAT_RTI_MEM_CORERR_SHIFT                                  (24U)
#define DPE_FUSA_INTSTAT_RTI_MEM_CORERR_WIDTH                                  (1U)
#define DPE_FUSA_INTSTAT_RTI_MEM_CORERR(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RTI_MEM_CORERR_SHIFT)) & DPE_FUSA_INTSTAT_RTI_MEM_CORERR_MASK)

/* DPE_FUSA_INTSTAT_AWREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_AWREADY_UNCERR_MASK                                   (0x2000000U)
#define DPE_FUSA_INTSTAT_AWREADY_UNCERR_SHIFT                                  (25U)
#define DPE_FUSA_INTSTAT_AWREADY_UNCERR_WIDTH                                  (1U)
#define DPE_FUSA_INTSTAT_AWREADY_UNCERR(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_AWREADY_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_AWREADY_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_LOCKSTEP_ERR Bit Fields */
#define DPE_FUSA_INTSTAT_LOCKSTEP_ERR_MASK                                     (0x4000000U)
#define DPE_FUSA_INTSTAT_LOCKSTEP_ERR_SHIFT                                    (26U)
#define DPE_FUSA_INTSTAT_LOCKSTEP_ERR_WIDTH                                    (1U)
#define DPE_FUSA_INTSTAT_LOCKSTEP_ERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_LOCKSTEP_ERR_SHIFT)) & DPE_FUSA_INTSTAT_LOCKSTEP_ERR_MASK)

/* DPE_FUSA_INTSTAT_RTC_FIFO_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_RTC_FIFO_UNCERR_MASK                                  (0x8000000U)
#define DPE_FUSA_INTSTAT_RTC_FIFO_UNCERR_SHIFT                                 (27U)
#define DPE_FUSA_INTSTAT_RTC_FIFO_UNCERR_WIDTH                                 (1U)
#define DPE_FUSA_INTSTAT_RTC_FIFO_UNCERR(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RTC_FIFO_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_RTC_FIFO_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_RTC_FIFO_CORERR Bit Fields */
#define DPE_FUSA_INTSTAT_RTC_FIFO_CORERR_MASK                                  (0x10000000U)
#define DPE_FUSA_INTSTAT_RTC_FIFO_CORERR_SHIFT                                 (28U)
#define DPE_FUSA_INTSTAT_RTC_FIFO_CORERR_WIDTH                                 (1U)
#define DPE_FUSA_INTSTAT_RTC_FIFO_CORERR(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_RTC_FIFO_CORERR_SHIFT)) & DPE_FUSA_INTSTAT_RTC_FIFO_CORERR_MASK)

/* DPE_FUSA_INTSTAT_QUEUE_FIFO_UNCERR Bit Fields */
#define DPE_FUSA_INTSTAT_QUEUE_FIFO_UNCERR_MASK                                (0x20000000U)
#define DPE_FUSA_INTSTAT_QUEUE_FIFO_UNCERR_SHIFT                               (29U)
#define DPE_FUSA_INTSTAT_QUEUE_FIFO_UNCERR_WIDTH                               (1U)
#define DPE_FUSA_INTSTAT_QUEUE_FIFO_UNCERR(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_QUEUE_FIFO_UNCERR_SHIFT)) & DPE_FUSA_INTSTAT_QUEUE_FIFO_UNCERR_MASK)

/* DPE_FUSA_INTSTAT_QUEUE_FIFO_CORERR Bit Fields */
#define DPE_FUSA_INTSTAT_QUEUE_FIFO_CORERR_MASK                                (0x40000000U)
#define DPE_FUSA_INTSTAT_QUEUE_FIFO_CORERR_SHIFT                               (30U)
#define DPE_FUSA_INTSTAT_QUEUE_FIFO_CORERR_WIDTH                               (1U)
#define DPE_FUSA_INTSTAT_QUEUE_FIFO_CORERR(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_QUEUE_FIFO_CORERR_SHIFT)) & DPE_FUSA_INTSTAT_QUEUE_FIFO_CORERR_MASK)

/* DPE_FUSA_INTSTAT_PACKET_CRC_ERR Bit Fields */
#define DPE_FUSA_INTSTAT_PACKET_CRC_ERR_MASK                                   (0x80000000U)
#define DPE_FUSA_INTSTAT_PACKET_CRC_ERR_SHIFT                                  (31U)
#define DPE_FUSA_INTSTAT_PACKET_CRC_ERR_WIDTH                                  (1U)
#define DPE_FUSA_INTSTAT_PACKET_CRC_ERR(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTSTAT_PACKET_CRC_ERR_SHIFT)) & DPE_FUSA_INTSTAT_PACKET_CRC_ERR_MASK)

/** register DPE_FUSA_INTCLR offset */
#define DPE_FUSA_INTCLR_OFFSET                                                 (0x2F38U)

/* DPE_FUSA_INTCLR_RTI_MEM_ECC_ERR Bit Fields */
#define DPE_FUSA_INTCLR_RTI_MEM_ECC_ERR_MASK                                   (0x1U)
#define DPE_FUSA_INTCLR_RTI_MEM_ECC_ERR_SHIFT                                  (0U)
#define DPE_FUSA_INTCLR_RTI_MEM_ECC_ERR_WIDTH                                  (1U)
#define DPE_FUSA_INTCLR_RTI_MEM_ECC_ERR(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RTI_MEM_ECC_ERR_SHIFT)) & DPE_FUSA_INTCLR_RTI_MEM_ECC_ERR_MASK)

/* DPE_FUSA_INTCLR_IN_SIG_ERR Bit Fields */
#define DPE_FUSA_INTCLR_IN_SIG_ERR_MASK                                        (0x2U)
#define DPE_FUSA_INTCLR_IN_SIG_ERR_SHIFT                                       (1U)
#define DPE_FUSA_INTCLR_IN_SIG_ERR_WIDTH                                       (1U)
#define DPE_FUSA_INTCLR_IN_SIG_ERR(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_IN_SIG_ERR_SHIFT)) & DPE_FUSA_INTCLR_IN_SIG_ERR_MASK)

/* DPE_FUSA_INTCLR_ARREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_ARREADY_UNCERR_MASK                                    (0x4U)
#define DPE_FUSA_INTCLR_ARREADY_UNCERR_SHIFT                                   (2U)
#define DPE_FUSA_INTCLR_ARREADY_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTCLR_ARREADY_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_ARREADY_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_ARREADY_UNCERR_MASK)

/* DPE_FUSA_INTCLR_BCTL_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_BCTL_UNCERR_MASK                                       (0x8U)
#define DPE_FUSA_INTCLR_BCTL_UNCERR_SHIFT                                      (3U)
#define DPE_FUSA_INTCLR_BCTL_UNCERR_WIDTH                                      (1U)
#define DPE_FUSA_INTCLR_BCTL_UNCERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_BCTL_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_BCTL_UNCERR_MASK)

/* DPE_FUSA_INTCLR_BID_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_BID_UNCERR_MASK                                        (0x10U)
#define DPE_FUSA_INTCLR_BID_UNCERR_SHIFT                                       (4U)
#define DPE_FUSA_INTCLR_BID_UNCERR_WIDTH                                       (1U)
#define DPE_FUSA_INTCLR_BID_UNCERR(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_BID_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_BID_UNCERR_MASK)

/* DPE_FUSA_INTCLR_BVALID_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_BVALID_UNCERR_MASK                                     (0x20U)
#define DPE_FUSA_INTCLR_BVALID_UNCERR_SHIFT                                    (5U)
#define DPE_FUSA_INTCLR_BVALID_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_BVALID_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_BVALID_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_BVALID_UNCERR_MASK)

/* DPE_FUSA_INTCLR_HRDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_HRDATA_UNCERR_MASK                                     (0x40U)
#define DPE_FUSA_INTCLR_HRDATA_UNCERR_SHIFT                                    (6U)
#define DPE_FUSA_INTCLR_HRDATA_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_HRDATA_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_HRDATA_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_HRDATA_UNCERR_MASK)

/* DPE_FUSA_INTCLR_HRDATA_FATAL Bit Fields */
#define DPE_FUSA_INTCLR_HRDATA_FATAL_MASK                                      (0x80U)
#define DPE_FUSA_INTCLR_HRDATA_FATAL_SHIFT                                     (7U)
#define DPE_FUSA_INTCLR_HRDATA_FATAL_WIDTH                                     (1U)
#define DPE_FUSA_INTCLR_HRDATA_FATAL(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_HRDATA_FATAL_SHIFT)) & DPE_FUSA_INTCLR_HRDATA_FATAL_MASK)

/* DPE_FUSA_INTCLR_HRESP_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_HRESP_UNCERR_MASK                                      (0x100U)
#define DPE_FUSA_INTCLR_HRESP_UNCERR_SHIFT                                     (8U)
#define DPE_FUSA_INTCLR_HRESP_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTCLR_HRESP_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_HRESP_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_HRESP_UNCERR_MASK)

/* DPE_FUSA_INTCLR_PADDR_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_PADDR_UNCERR_MASK                                      (0x200U)
#define DPE_FUSA_INTCLR_PADDR_UNCERR_SHIFT                                     (9U)
#define DPE_FUSA_INTCLR_PADDR_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTCLR_PADDR_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_PADDR_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_PADDR_UNCERR_MASK)

/* DPE_FUSA_INTCLR_PCTRL0_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_PCTRL0_UNCERR_MASK                                     (0x400U)
#define DPE_FUSA_INTCLR_PCTRL0_UNCERR_SHIFT                                    (10U)
#define DPE_FUSA_INTCLR_PCTRL0_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_PCTRL0_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_PCTRL0_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_PCTRL0_UNCERR_MASK)

/* DPE_FUSA_INTCLR_PCTRL1_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_PCTRL1_UNCERR_MASK                                     (0x800U)
#define DPE_FUSA_INTCLR_PCTRL1_UNCERR_SHIFT                                    (11U)
#define DPE_FUSA_INTCLR_PCTRL1_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_PCTRL1_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_PCTRL1_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_PCTRL1_UNCERR_MASK)

/* DPE_FUSA_INTCLR_PWDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_PWDATA_UNCERR_MASK                                     (0x1000U)
#define DPE_FUSA_INTCLR_PWDATA_UNCERR_SHIFT                                    (12U)
#define DPE_FUSA_INTCLR_PWDATA_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_PWDATA_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_PWDATA_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_PWDATA_UNCERR_MASK)

/* DPE_FUSA_INTCLR_PWDATA_FATAL Bit Fields */
#define DPE_FUSA_INTCLR_PWDATA_FATAL_MASK                                      (0x2000U)
#define DPE_FUSA_INTCLR_PWDATA_FATAL_SHIFT                                     (13U)
#define DPE_FUSA_INTCLR_PWDATA_FATAL_WIDTH                                     (1U)
#define DPE_FUSA_INTCLR_PWDATA_FATAL(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_PWDATA_FATAL_SHIFT)) & DPE_FUSA_INTCLR_PWDATA_FATAL_MASK)

/* DPE_FUSA_INTCLR_RCTL_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_RCTL_UNCERR_MASK                                       (0x4000U)
#define DPE_FUSA_INTCLR_RCTL_UNCERR_SHIFT                                      (14U)
#define DPE_FUSA_INTCLR_RCTL_UNCERR_WIDTH                                      (1U)
#define DPE_FUSA_INTCLR_RCTL_UNCERR(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RCTL_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_RCTL_UNCERR_MASK)

/* DPE_FUSA_INTCLR_RID_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_RID_UNCERR_MASK                                        (0x8000U)
#define DPE_FUSA_INTCLR_RID_UNCERR_SHIFT                                       (15U)
#define DPE_FUSA_INTCLR_RID_UNCERR_WIDTH                                       (1U)
#define DPE_FUSA_INTCLR_RID_UNCERR(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RID_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_RID_UNCERR_MASK)

/* DPE_FUSA_INTCLR_RDATA_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_RDATA_UNCERR_MASK                                      (0x10000U)
#define DPE_FUSA_INTCLR_RDATA_UNCERR_SHIFT                                     (16U)
#define DPE_FUSA_INTCLR_RDATA_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTCLR_RDATA_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RDATA_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_RDATA_UNCERR_MASK)

/* DPE_FUSA_INTCLR_RVALID_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_RVALID_UNCERR_MASK                                     (0x20000U)
#define DPE_FUSA_INTCLR_RVALID_UNCERR_SHIFT                                    (17U)
#define DPE_FUSA_INTCLR_RVALID_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_RVALID_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RVALID_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_RVALID_UNCERR_MASK)

/* DPE_FUSA_INTCLR_RDATA_FATAL Bit Fields */
#define DPE_FUSA_INTCLR_RDATA_FATAL_MASK                                       (0x40000U)
#define DPE_FUSA_INTCLR_RDATA_FATAL_SHIFT                                      (18U)
#define DPE_FUSA_INTCLR_RDATA_FATAL_WIDTH                                      (1U)
#define DPE_FUSA_INTCLR_RDATA_FATAL(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RDATA_FATAL_SHIFT)) & DPE_FUSA_INTCLR_RDATA_FATAL_MASK)

/* DPE_FUSA_INTCLR_WREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_WREADY_UNCERR_MASK                                     (0x80000U)
#define DPE_FUSA_INTCLR_WREADY_UNCERR_SHIFT                                    (19U)
#define DPE_FUSA_INTCLR_WREADY_UNCERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_WREADY_UNCERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_WREADY_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_WREADY_UNCERR_MASK)

/* DPE_FUSA_INTCLR_REOBI_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_REOBI_UNCERR_MASK                                      (0x100000U)
#define DPE_FUSA_INTCLR_REOBI_UNCERR_SHIFT                                     (20U)
#define DPE_FUSA_INTCLR_REOBI_UNCERR_WIDTH                                     (1U)
#define DPE_FUSA_INTCLR_REOBI_UNCERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_REOBI_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_REOBI_UNCERR_MASK)

/* DPE_FUSA_INTCLR_HRDATA_CORERR Bit Fields */
#define DPE_FUSA_INTCLR_HRDATA_CORERR_MASK                                     (0x200000U)
#define DPE_FUSA_INTCLR_HRDATA_CORERR_SHIFT                                    (21U)
#define DPE_FUSA_INTCLR_HRDATA_CORERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_HRDATA_CORERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_HRDATA_CORERR_SHIFT)) & DPE_FUSA_INTCLR_HRDATA_CORERR_MASK)

/* DPE_FUSA_INTCLR_PWDATA_CORERR Bit Fields */
#define DPE_FUSA_INTCLR_PWDATA_CORERR_MASK                                     (0x400000U)
#define DPE_FUSA_INTCLR_PWDATA_CORERR_SHIFT                                    (22U)
#define DPE_FUSA_INTCLR_PWDATA_CORERR_WIDTH                                    (1U)
#define DPE_FUSA_INTCLR_PWDATA_CORERR(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_PWDATA_CORERR_SHIFT)) & DPE_FUSA_INTCLR_PWDATA_CORERR_MASK)

/* DPE_FUSA_INTCLR_RDATA_CORERR Bit Fields */
#define DPE_FUSA_INTCLR_RDATA_CORERR_MASK                                      (0x800000U)
#define DPE_FUSA_INTCLR_RDATA_CORERR_SHIFT                                     (23U)
#define DPE_FUSA_INTCLR_RDATA_CORERR_WIDTH                                     (1U)
#define DPE_FUSA_INTCLR_RDATA_CORERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RDATA_CORERR_SHIFT)) & DPE_FUSA_INTCLR_RDATA_CORERR_MASK)

/* DPE_FUSA_INTCLR_RTI_MEM_CORERR Bit Fields */
#define DPE_FUSA_INTCLR_RTI_MEM_CORERR_MASK                                    (0x1000000U)
#define DPE_FUSA_INTCLR_RTI_MEM_CORERR_SHIFT                                   (24U)
#define DPE_FUSA_INTCLR_RTI_MEM_CORERR_WIDTH                                   (1U)
#define DPE_FUSA_INTCLR_RTI_MEM_CORERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RTI_MEM_CORERR_SHIFT)) & DPE_FUSA_INTCLR_RTI_MEM_CORERR_MASK)

/* DPE_FUSA_INTCLR_AWREADY_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_AWREADY_UNCERR_MASK                                    (0x2000000U)
#define DPE_FUSA_INTCLR_AWREADY_UNCERR_SHIFT                                   (25U)
#define DPE_FUSA_INTCLR_AWREADY_UNCERR_WIDTH                                   (1U)
#define DPE_FUSA_INTCLR_AWREADY_UNCERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_AWREADY_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_AWREADY_UNCERR_MASK)

/* DPE_FUSA_INTCLR_LOCKSTEP_ERR Bit Fields */
#define DPE_FUSA_INTCLR_LOCKSTEP_ERR_MASK                                      (0x4000000U)
#define DPE_FUSA_INTCLR_LOCKSTEP_ERR_SHIFT                                     (26U)
#define DPE_FUSA_INTCLR_LOCKSTEP_ERR_WIDTH                                     (1U)
#define DPE_FUSA_INTCLR_LOCKSTEP_ERR(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_LOCKSTEP_ERR_SHIFT)) & DPE_FUSA_INTCLR_LOCKSTEP_ERR_MASK)

/* DPE_FUSA_INTCLR_RTC_FIFO_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_RTC_FIFO_UNCERR_MASK                                   (0x8000000U)
#define DPE_FUSA_INTCLR_RTC_FIFO_UNCERR_SHIFT                                  (27U)
#define DPE_FUSA_INTCLR_RTC_FIFO_UNCERR_WIDTH                                  (1U)
#define DPE_FUSA_INTCLR_RTC_FIFO_UNCERR(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RTC_FIFO_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_RTC_FIFO_UNCERR_MASK)

/* DPE_FUSA_INTCLR_RTC_FIFO_CORERR Bit Fields */
#define DPE_FUSA_INTCLR_RTC_FIFO_CORERR_MASK                                   (0x10000000U)
#define DPE_FUSA_INTCLR_RTC_FIFO_CORERR_SHIFT                                  (28U)
#define DPE_FUSA_INTCLR_RTC_FIFO_CORERR_WIDTH                                  (1U)
#define DPE_FUSA_INTCLR_RTC_FIFO_CORERR(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_RTC_FIFO_CORERR_SHIFT)) & DPE_FUSA_INTCLR_RTC_FIFO_CORERR_MASK)

/* DPE_FUSA_INTCLR_QUEUE_FIFO_UNCERR Bit Fields */
#define DPE_FUSA_INTCLR_QUEUE_FIFO_UNCERR_MASK                                 (0x20000000U)
#define DPE_FUSA_INTCLR_QUEUE_FIFO_UNCERR_SHIFT                                (29U)
#define DPE_FUSA_INTCLR_QUEUE_FIFO_UNCERR_WIDTH                                (1U)
#define DPE_FUSA_INTCLR_QUEUE_FIFO_UNCERR(x)                                   (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_QUEUE_FIFO_UNCERR_SHIFT)) & DPE_FUSA_INTCLR_QUEUE_FIFO_UNCERR_MASK)

/* DPE_FUSA_INTCLR_QUEUE_FIFO_CORERR Bit Fields */
#define DPE_FUSA_INTCLR_QUEUE_FIFO_CORERR_MASK                                 (0x40000000U)
#define DPE_FUSA_INTCLR_QUEUE_FIFO_CORERR_SHIFT                                (30U)
#define DPE_FUSA_INTCLR_QUEUE_FIFO_CORERR_WIDTH                                (1U)
#define DPE_FUSA_INTCLR_QUEUE_FIFO_CORERR(x)                                   (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_QUEUE_FIFO_CORERR_SHIFT)) & DPE_FUSA_INTCLR_QUEUE_FIFO_CORERR_MASK)

/* DPE_FUSA_INTCLR_PACKET_CRC_ERR Bit Fields */
#define DPE_FUSA_INTCLR_PACKET_CRC_ERR_MASK                                    (0x80000000U)
#define DPE_FUSA_INTCLR_PACKET_CRC_ERR_SHIFT                                   (31U)
#define DPE_FUSA_INTCLR_PACKET_CRC_ERR_WIDTH                                   (1U)
#define DPE_FUSA_INTCLR_PACKET_CRC_ERR(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_FUSA_INTCLR_PACKET_CRC_ERR_SHIFT)) & DPE_FUSA_INTCLR_PACKET_CRC_ERR_MASK)

/** register DPE_E2E_ERR_INJ_CTRL offset */
#define DPE_E2E_ERR_INJ_CTRL_OFFSET                                            (0x2F3CU)

/* DPE_E2E_ERR_INJ_CTRL_APB_ERR_INJ_EN Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_APB_ERR_INJ_EN_MASK                               (0x1U)
#define DPE_E2E_ERR_INJ_CTRL_APB_ERR_INJ_EN_SHIFT                              (0U)
#define DPE_E2E_ERR_INJ_CTRL_APB_ERR_INJ_EN_WIDTH                              (1U)
#define DPE_E2E_ERR_INJ_CTRL_APB_ERR_INJ_EN(x)                                 (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_APB_ERR_INJ_EN_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_APB_ERR_INJ_EN_MASK)

/* DPE_E2E_ERR_INJ_CTRL_AXI_RDATA_ERR_INJ_EN Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_AXI_RDATA_ERR_INJ_EN_MASK                         (0x2U)
#define DPE_E2E_ERR_INJ_CTRL_AXI_RDATA_ERR_INJ_EN_SHIFT                        (1U)
#define DPE_E2E_ERR_INJ_CTRL_AXI_RDATA_ERR_INJ_EN_WIDTH                        (1U)
#define DPE_E2E_ERR_INJ_CTRL_AXI_RDATA_ERR_INJ_EN(x)                           (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_AXI_RDATA_ERR_INJ_EN_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_AXI_RDATA_ERR_INJ_EN_MASK)

/* DPE_E2E_ERR_INJ_CTRL_AHB_RDATA_ERR_INJ_EN Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_AHB_RDATA_ERR_INJ_EN_MASK                         (0x4U)
#define DPE_E2E_ERR_INJ_CTRL_AHB_RDATA_ERR_INJ_EN_SHIFT                        (2U)
#define DPE_E2E_ERR_INJ_CTRL_AHB_RDATA_ERR_INJ_EN_WIDTH                        (1U)
#define DPE_E2E_ERR_INJ_CTRL_AHB_RDATA_ERR_INJ_EN(x)                           (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_AHB_RDATA_ERR_INJ_EN_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_AHB_RDATA_ERR_INJ_EN_MASK)

/* DPE_E2E_ERR_INJ_CTRL_DPE_IRQ_ERR_INJ_EN Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_DPE_IRQ_ERR_INJ_EN_MASK                           (0x8U)
#define DPE_E2E_ERR_INJ_CTRL_DPE_IRQ_ERR_INJ_EN_SHIFT                          (3U)
#define DPE_E2E_ERR_INJ_CTRL_DPE_IRQ_ERR_INJ_EN_WIDTH                          (1U)
#define DPE_E2E_ERR_INJ_CTRL_DPE_IRQ_ERR_INJ_EN(x)                             (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_DPE_IRQ_ERR_INJ_EN_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_DPE_IRQ_ERR_INJ_EN_MASK)

/* DPE_E2E_ERR_INJ_CTRL_RTI_MEM_ECC_ERR_INJ_EN Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_RTI_MEM_ECC_ERR_INJ_EN_MASK                       (0x10U)
#define DPE_E2E_ERR_INJ_CTRL_RTI_MEM_ECC_ERR_INJ_EN_SHIFT                      (4U)
#define DPE_E2E_ERR_INJ_CTRL_RTI_MEM_ECC_ERR_INJ_EN_WIDTH                      (1U)
#define DPE_E2E_ERR_INJ_CTRL_RTI_MEM_ECC_ERR_INJ_EN(x)                         (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_RTI_MEM_ECC_ERR_INJ_EN_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_RTI_MEM_ECC_ERR_INJ_EN_MASK)

/* DPE_E2E_ERR_INJ_CTRL_FIFO_ECC_ERR_INJ_EN Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_FIFO_ECC_ERR_INJ_EN_MASK                          (0x20U)
#define DPE_E2E_ERR_INJ_CTRL_FIFO_ECC_ERR_INJ_EN_SHIFT                         (5U)
#define DPE_E2E_ERR_INJ_CTRL_FIFO_ECC_ERR_INJ_EN_WIDTH                         (1U)
#define DPE_E2E_ERR_INJ_CTRL_FIFO_ECC_ERR_INJ_EN(x)                            (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_FIFO_ECC_ERR_INJ_EN_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_FIFO_ECC_ERR_INJ_EN_MASK)

/* DPE_E2E_ERR_INJ_CTRL_MEM_INTEGRITY_CHK_ERR_INJ Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_MEM_INTEGRITY_CHK_ERR_INJ_MASK                    (0x40U)
#define DPE_E2E_ERR_INJ_CTRL_MEM_INTEGRITY_CHK_ERR_INJ_SHIFT                   (6U)
#define DPE_E2E_ERR_INJ_CTRL_MEM_INTEGRITY_CHK_ERR_INJ_WIDTH                   (1U)
#define DPE_E2E_ERR_INJ_CTRL_MEM_INTEGRITY_CHK_ERR_INJ(x)                      (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_MEM_INTEGRITY_CHK_ERR_INJ_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_MEM_INTEGRITY_CHK_ERR_INJ_MASK)

/* DPE_E2E_ERR_INJ_CTRL_QUEUE_FIFO_ERR_INJ_EN Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_QUEUE_FIFO_ERR_INJ_EN_MASK                        (0x80U)
#define DPE_E2E_ERR_INJ_CTRL_QUEUE_FIFO_ERR_INJ_EN_SHIFT                       (7U)
#define DPE_E2E_ERR_INJ_CTRL_QUEUE_FIFO_ERR_INJ_EN_WIDTH                       (1U)
#define DPE_E2E_ERR_INJ_CTRL_QUEUE_FIFO_ERR_INJ_EN(x)                          (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_QUEUE_FIFO_ERR_INJ_EN_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_QUEUE_FIFO_ERR_INJ_EN_MASK)

/* DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL1 Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL1_MASK                            (0x1FF00U)
#define DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL1_SHIFT                           (8U)
#define DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL1_WIDTH                           (9U)
#define DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL1(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL1_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL1_MASK)

/* DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL2 Bit Fields */
#define DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL2_MASK                            (0x3FE0000U)
#define DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL2_SHIFT                           (17U)
#define DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL2_WIDTH                           (9U)
#define DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL2(x)                              (((uint32_t)(((uint32_t)(x)) << DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL2_SHIFT)) & DPE_E2E_ERR_INJ_CTRL_DATA_ERR_INJ_SEL2_MASK)

/** register DPE_DVCANINTEN offset */
#define DPE_DVCANINTEN_OFFSET                                                  (0x2F40U)

/* DPE_DVCANINTEN_DVCAN_REC Bit Fields */
#define DPE_DVCANINTEN_DVCAN_REC_MASK                                          (0x1U)
#define DPE_DVCANINTEN_DVCAN_REC_SHIFT                                         (0U)
#define DPE_DVCANINTEN_DVCAN_REC_WIDTH                                         (1U)
#define DPE_DVCANINTEN_DVCAN_REC(x)                                            (((uint32_t)(((uint32_t)(x)) << DPE_DVCANINTEN_DVCAN_REC_SHIFT)) & DPE_DVCANINTEN_DVCAN_REC_MASK)

/* DPE_DVCANINTEN_DVCAN_REC_DROP Bit Fields */
#define DPE_DVCANINTEN_DVCAN_REC_DROP_MASK                                     (0x2U)
#define DPE_DVCANINTEN_DVCAN_REC_DROP_SHIFT                                    (1U)
#define DPE_DVCANINTEN_DVCAN_REC_DROP_WIDTH                                    (1U)
#define DPE_DVCANINTEN_DVCAN_REC_DROP(x)                                       (((uint32_t)(((uint32_t)(x)) << DPE_DVCANINTEN_DVCAN_REC_DROP_SHIFT)) & DPE_DVCANINTEN_DVCAN_REC_DROP_MASK)

/** register DPE_DVCANINTSTAT offset */
#define DPE_DVCANINTSTAT_OFFSET                                                (0x2F44U)

/* DPE_DVCANINTSTAT_DVCAN_REC Bit Fields */
#define DPE_DVCANINTSTAT_DVCAN_REC_MASK                                        (0x1U)
#define DPE_DVCANINTSTAT_DVCAN_REC_SHIFT                                       (0U)
#define DPE_DVCANINTSTAT_DVCAN_REC_WIDTH                                       (1U)
#define DPE_DVCANINTSTAT_DVCAN_REC(x)                                          (((uint32_t)(((uint32_t)(x)) << DPE_DVCANINTSTAT_DVCAN_REC_SHIFT)) & DPE_DVCANINTSTAT_DVCAN_REC_MASK)

/* DPE_DVCANINTSTAT_DVCAN_REC_DROP Bit Fields */
#define DPE_DVCANINTSTAT_DVCAN_REC_DROP_MASK                                   (0x2U)
#define DPE_DVCANINTSTAT_DVCAN_REC_DROP_SHIFT                                  (1U)
#define DPE_DVCANINTSTAT_DVCAN_REC_DROP_WIDTH                                  (1U)
#define DPE_DVCANINTSTAT_DVCAN_REC_DROP(x)                                     (((uint32_t)(((uint32_t)(x)) << DPE_DVCANINTSTAT_DVCAN_REC_DROP_SHIFT)) & DPE_DVCANINTSTAT_DVCAN_REC_DROP_MASK)

/** register DPE_DVCANINTCLR offset */
#define DPE_DVCANINTCLR_OFFSET                                                 (0x2F48U)

/* DPE_DVCANINTCLR_DVCAN_REC Bit Fields */
#define DPE_DVCANINTCLR_DVCAN_REC_MASK                                         (0x1U)
#define DPE_DVCANINTCLR_DVCAN_REC_SHIFT                                        (0U)
#define DPE_DVCANINTCLR_DVCAN_REC_WIDTH                                        (1U)
#define DPE_DVCANINTCLR_DVCAN_REC(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_DVCANINTCLR_DVCAN_REC_SHIFT)) & DPE_DVCANINTCLR_DVCAN_REC_MASK)

/* DPE_DVCANINTCLR_DVCAN_REC_DROP Bit Fields */
#define DPE_DVCANINTCLR_DVCAN_REC_DROP_MASK                                    (0x2U)
#define DPE_DVCANINTCLR_DVCAN_REC_DROP_SHIFT                                   (1U)
#define DPE_DVCANINTCLR_DVCAN_REC_DROP_WIDTH                                   (1U)
#define DPE_DVCANINTCLR_DVCAN_REC_DROP(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_DVCANINTCLR_DVCAN_REC_DROP_SHIFT)) & DPE_DVCANINTCLR_DVCAN_REC_DROP_MASK)

/** register DPE_LOCKSTEP_ERR_INJ_CTRL offset */
#define DPE_LOCKSTEP_ERR_INJ_CTRL_OFFSET                                       (0x2F50U)

/* DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_SEL Bit Fields */
#define DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_SEL_MASK                             (0x7FFFFFFFU)
#define DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_SEL_SHIFT                            (0U)
#define DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_SEL_WIDTH                            (31U)
#define DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_SEL(x)                               (((uint32_t)(((uint32_t)(x)) << DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_SEL_SHIFT)) & DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_SEL_MASK)

/* DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_EN Bit Fields */
#define DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_EN_MASK                              (0x80000000U)
#define DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_EN_SHIFT                             (31U)
#define DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_EN_WIDTH                             (1U)
#define DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_EN(x)                                (((uint32_t)(((uint32_t)(x)) << DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_EN_SHIFT)) & DPE_LOCKSTEP_ERR_INJ_CTRL_ERR_INJ_EN_MASK)

/** register DPE_LOCKSTEP_ERR_STAT offset */
#define DPE_LOCKSTEP_ERR_STAT_OFFSET                                           (0x2F54U)

/* DPE_LOCKSTEP_ERR_STAT_ERR_STAT Bit Fields */
#define DPE_LOCKSTEP_ERR_STAT_ERR_STAT_MASK                                    (0xFFFFFFFFU)
#define DPE_LOCKSTEP_ERR_STAT_ERR_STAT_SHIFT                                   (0U)
#define DPE_LOCKSTEP_ERR_STAT_ERR_STAT_WIDTH                                   (32U)
#define DPE_LOCKSTEP_ERR_STAT_ERR_STAT(x)                                      (((uint32_t)(((uint32_t)(x)) << DPE_LOCKSTEP_ERR_STAT_ERR_STAT_SHIFT)) & DPE_LOCKSTEP_ERR_STAT_ERR_STAT_MASK)

/** register DPE_DEBUG_BUS_SEL offset */
#define DPE_DEBUG_BUS_SEL_OFFSET                                               (0x2FA0U)

/* DPE_DEBUG_BUS_SEL_SEL Bit Fields */
#define DPE_DEBUG_BUS_SEL_SEL_MASK                                             (0xFU)
#define DPE_DEBUG_BUS_SEL_SEL_SHIFT                                            (0U)
#define DPE_DEBUG_BUS_SEL_SEL_WIDTH                                            (4U)
#define DPE_DEBUG_BUS_SEL_SEL(x)                                               (((uint32_t)(((uint32_t)(x)) << DPE_DEBUG_BUS_SEL_SEL_SHIFT)) & DPE_DEBUG_BUS_SEL_SEL_MASK)

/** register DPE_DEBUG_BUS_STATUS offset */
#define DPE_DEBUG_BUS_STATUS_OFFSET                                            (0x2FA4U)

/* DPE_DEBUG_BUS_STATUS_STATUS Bit Fields */
#define DPE_DEBUG_BUS_STATUS_STATUS_MASK                                       (0xFFFFFFFFU)
#define DPE_DEBUG_BUS_STATUS_STATUS_SHIFT                                      (0U)
#define DPE_DEBUG_BUS_STATUS_STATUS_WIDTH                                      (32U)
#define DPE_DEBUG_BUS_STATUS_STATUS(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_DEBUG_BUS_STATUS_STATUS_SHIFT)) & DPE_DEBUG_BUS_STATUS_STATUS_MASK)

/** register DPE_DROP_FRAMEID offset */
#define DPE_DROP_FRAMEID_OFFSET                                                (0x2FA8U)

/* DPE_DROP_FRAMEID_FRAMEID Bit Fields */
#define DPE_DROP_FRAMEID_FRAMEID_MASK                                          (0x1FFFFFFFU)
#define DPE_DROP_FRAMEID_FRAMEID_SHIFT                                         (0U)
#define DPE_DROP_FRAMEID_FRAMEID_WIDTH                                         (29U)
#define DPE_DROP_FRAMEID_FRAMEID(x)                                            (((uint32_t)(((uint32_t)(x)) << DPE_DROP_FRAMEID_FRAMEID_SHIFT)) & DPE_DROP_FRAMEID_FRAMEID_MASK)

/** register DPE_DROP_FRAME_SRC_BUSID offset */
#define DPE_DROP_FRAME_SRC_BUSID_OFFSET                                        (0x2FACU)

/* DPE_DROP_FRAME_SRC_BUSID_SRC_BUSID Bit Fields */
#define DPE_DROP_FRAME_SRC_BUSID_SRC_BUSID_MASK                                (0x3FU)
#define DPE_DROP_FRAME_SRC_BUSID_SRC_BUSID_SHIFT                               (0U)
#define DPE_DROP_FRAME_SRC_BUSID_SRC_BUSID_WIDTH                               (6U)
#define DPE_DROP_FRAME_SRC_BUSID_SRC_BUSID(x)                                  (((uint32_t)(((uint32_t)(x)) << DPE_DROP_FRAME_SRC_BUSID_SRC_BUSID_SHIFT)) & DPE_DROP_FRAME_SRC_BUSID_SRC_BUSID_MASK)

/** register DPE_REVISION offset */
#define DPE_REVISION_OFFSET                                                    (0x2FF0U)

/* DPE_REVISION_PHASE_REVISION Bit Fields */
#define DPE_REVISION_PHASE_REVISION_MASK                                       (0xFFU)
#define DPE_REVISION_PHASE_REVISION_SHIFT                                      (0U)
#define DPE_REVISION_PHASE_REVISION_WIDTH                                      (8U)
#define DPE_REVISION_PHASE_REVISION(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_REVISION_PHASE_REVISION_SHIFT)) & DPE_REVISION_PHASE_REVISION_MASK)

/* DPE_REVISION_MINOR_REVISION Bit Fields */
#define DPE_REVISION_MINOR_REVISION_MASK                                       (0xFF00U)
#define DPE_REVISION_MINOR_REVISION_SHIFT                                      (8U)
#define DPE_REVISION_MINOR_REVISION_WIDTH                                      (8U)
#define DPE_REVISION_MINOR_REVISION(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_REVISION_MINOR_REVISION_SHIFT)) & DPE_REVISION_MINOR_REVISION_MASK)

/* DPE_REVISION_MAJOR_REVISION Bit Fields */
#define DPE_REVISION_MAJOR_REVISION_MASK                                       (0xFF0000U)
#define DPE_REVISION_MAJOR_REVISION_SHIFT                                      (16U)
#define DPE_REVISION_MAJOR_REVISION_WIDTH                                      (8U)
#define DPE_REVISION_MAJOR_REVISION(x)                                         (((uint32_t)(((uint32_t)(x)) << DPE_REVISION_MAJOR_REVISION_SHIFT)) & DPE_REVISION_MAJOR_REVISION_MASK)

/** register DPE_CONFIG_PARAM offset */
#define DPE_CONFIG_PARAM_OFFSET                                                (0x2FF4U)

/* DPE_CONFIG_PARAM_ROUTING_RULE_NUM Bit Fields */
#define DPE_CONFIG_PARAM_ROUTING_RULE_NUM_MASK                                 (0xFU)
#define DPE_CONFIG_PARAM_ROUTING_RULE_NUM_SHIFT                                (0U)
#define DPE_CONFIG_PARAM_ROUTING_RULE_NUM_WIDTH                                (4U)
#define DPE_CONFIG_PARAM_ROUTING_RULE_NUM(x)                                   (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_PARAM_ROUTING_RULE_NUM_SHIFT)) & DPE_CONFIG_PARAM_ROUTING_RULE_NUM_MASK)

/* DPE_CONFIG_PARAM_QUEUE_DEPTH Bit Fields */
#define DPE_CONFIG_PARAM_QUEUE_DEPTH_MASK                                      (0xF0U)
#define DPE_CONFIG_PARAM_QUEUE_DEPTH_SHIFT                                     (4U)
#define DPE_CONFIG_PARAM_QUEUE_DEPTH_WIDTH                                     (4U)
#define DPE_CONFIG_PARAM_QUEUE_DEPTH(x)                                        (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_PARAM_QUEUE_DEPTH_SHIFT)) & DPE_CONFIG_PARAM_QUEUE_DEPTH_MASK)

/* DPE_CONFIG_PARAM_VCAN_NUM Bit Fields */
#define DPE_CONFIG_PARAM_VCAN_NUM_MASK                                         (0xFF00U)
#define DPE_CONFIG_PARAM_VCAN_NUM_SHIFT                                        (8U)
#define DPE_CONFIG_PARAM_VCAN_NUM_WIDTH                                        (8U)
#define DPE_CONFIG_PARAM_VCAN_NUM(x)                                           (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_PARAM_VCAN_NUM_SHIFT)) & DPE_CONFIG_PARAM_VCAN_NUM_MASK)

/* DPE_CONFIG_PARAM_VCAN_FIFO_DEPTH Bit Fields */
#define DPE_CONFIG_PARAM_VCAN_FIFO_DEPTH_MASK                                  (0xFF0000U)
#define DPE_CONFIG_PARAM_VCAN_FIFO_DEPTH_SHIFT                                 (16U)
#define DPE_CONFIG_PARAM_VCAN_FIFO_DEPTH_WIDTH                                 (8U)
#define DPE_CONFIG_PARAM_VCAN_FIFO_DEPTH(x)                                    (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_PARAM_VCAN_FIFO_DEPTH_SHIFT)) & DPE_CONFIG_PARAM_VCAN_FIFO_DEPTH_MASK)

/* DPE_CONFIG_PARAM_PFC_NUM Bit Fields */
#define DPE_CONFIG_PARAM_PFC_NUM_MASK                                          (0xFF000000U)
#define DPE_CONFIG_PARAM_PFC_NUM_SHIFT                                         (24U)
#define DPE_CONFIG_PARAM_PFC_NUM_WIDTH                                         (8U)
#define DPE_CONFIG_PARAM_PFC_NUM(x)                                            (((uint32_t)(((uint32_t)(x)) << DPE_CONFIG_PARAM_PFC_NUM_SHIFT)) & DPE_CONFIG_PARAM_PFC_NUM_MASK)

#define DPE_RTLB_INDEX_ADDR_START_OFFSET (0x8000U)
#define DPE_RTLB_INDEX_ADDR_END_OFFSET (DPE_RTLB_INDEX_ADDR_START_OFFSET + DPE_MAX_RTLB_INDEX_SIZE)

#define DPE_SUBQUEUE_CONFIG_SQ_ARBIT_SCHEME_MASK (0x3U)
#define DPE_SUBQUEUE_CONFIG_SQ_ARBIT_SCHEME_SHIFT (0U)
#define DPE_SUBQUEUE_CONFIG_SQ_REPLACE_EN_MASK (0x4U)
#define DPE_SUBQUEUE_CONFIG_SQ_REPLACE_EN_SHIFT (2U)
#define DPE_SUBQUEUE_CONFIG_MASK (DPE_SUBQUEUE_CONFIG_SQ_ARBIT_SCHEME_MASK | DPE_SUBQUEUE_CONFIG_SQ_REPLACE_EN_MASK)

#define DPE_CAN_SUBQUEUE_CONFIG_SQ_ARBIT_SCHEME(x, i) ((uint32_t)(((uint32_t)(x)) & DPE_SUBQUEUE_CONFIG_SQ_ARBIT_SCHEME_MASK) << (i * 4U))
#define DPE_CAN_SUBQUEUE_CONFIG_SQ_REPLACE_EN(x, i) ((uint32_t)(((uint32_t)(x)) & DPE_SUBQUEUE_CONFIG_SQ_REPLACE_EN_MASK) << (i * 4U))


/*!
 * @}
 */ /* end of group DPE Register Masks */


/* Confirm theoretical polling counter and actual execution time. */
#define DPE_EN_TIMEOUT_COUNTER (100000U)

/* DPE time counter uint */
#define DPE_TIME_COUNTER_UNIT_VAL (100U)

/* Set a relatively small timeout value so that when timeout is dynamically enabled,
 * VCAN can receive send timeout status as early as possible.
 */
#define DPE_CAN_TXQUEUE_TIMEOUT_CNT (1U)

/* If DPE_CONVERT_ENDIAN is set to 0, the endianness of DPE packet is converted by DPE. */
#define DPE_CONVERT_ENDIAN 0

#if DPE_CONVERT_ENDIAN
#define DPE_IDX_CONVERT(x)  (((x) & 0xFCU) + 3U - ((x) & 3U))
#else
#define DPE_IDX_CONVERT(x)  (x)
#endif

#ifndef IS_ALIGNED
#define IS_ALIGNED(a, b) (!(((uintptr_t)(a)) & (((uintptr_t)(b))-1)))
#endif

/* Get packet buffer fields. */
#define PACKET_HEADER_FIELD(x) (*(x))
#define PACKET_ID_FIELD(x) (*((x) + 1))
#define PACKET_DATA_FIELD(x) ((uint32_t *)((x) + 2))
#define PACKET_TAIL_FIELD(x) (*((x) + 18))

#define PACKET_BUFFER_DLC_MASK (0xF0000U)
#define PACKET_BUFFER_DLC_SHIFT (16U)
#define PACKET_BUFFER_DLC(x) (((uint32_t)(((uint32_t)(x)) << PACKET_BUFFER_DLC_SHIFT)) & PACKET_BUFFER_DLC_MASK)
#define PACKET_BUFFER_IDE_MASK (0x200000U)
#define PACKET_BUFFER_IDE_SHIFT (21U)
#define PACKET_BUFFER_IDE(x) (((uint32_t)(((uint32_t)(x)) << PACKET_BUFFER_IDE_SHIFT)) & PACKET_BUFFER_IDE_MASK)
#define PACKET_BUFFER_EDL_MASK (0x80000000U)
#define PACKET_BUFFER_EDL_SHIFT (31U)
#define PACKET_BUFFER_EDL(x) (((uint32_t)(((uint32_t)(x)) << PACKET_BUFFER_EDL_SHIFT)) & PACKET_BUFFER_EDL_MASK)
#define PACKET_BUFFER_CAN_ID_EXT_MASK (0x1FFFFFFFU)
#define PACKET_BUFFER_CAN_ID_EXT_SHIFT (0U)
#define PACKET_BUFFER_CAN_ID_EXT(x)                                                          \
    (((uint32_t)(((uint32_t)(x)) << PACKET_BUFFER_CAN_ID_EXT_SHIFT)) & PACKET_BUFFER_CAN_ID_EXT_MASK)
#define PACKET_BUFFER_CAN_ID_STD_MASK (0x1FFC0000U)
#define PACKET_BUFFER_CAN_ID_STD_SHIFT (18U)
#define PACKET_BUFFER_CAN_ID_STD(x)                                                          \
    (((uint32_t)(((uint32_t)(x)) << PACKET_BUFFER_CAN_ID_STD_SHIFT)) & PACKET_BUFFER_CAN_ID_STD_MASK)
#define PACKET_BUFFER_PKT_ID_MASK (0xFFFFFFU)
#define PACKET_BUFFER_PKT_ID_SHIFT (0U)
#define PACKET_BUFFER_PKT_ID(x) (((uint32_t)(((uint32_t)(x)) << PACKET_BUFFER_PKT_ID_SHIFT)) & PACKET_BUFFER_PKT_ID_MASK)
#if DPE_CONVERT_ENDIAN
#define PACKET_BUFFER_SRC_BUS_MASK (0x3F000000U)
#define PACKET_BUFFER_SRC_BUS_SHIFT (24U)
#else
#define PACKET_BUFFER_SRC_BUS_MASK (0x3FU)
#define PACKET_BUFFER_SRC_BUS_SHIFT (0U)
#endif
#define PACKET_BUFFER_SRC_BUS(x) (((uint32_t)(((uint32_t)(x)) << PACKET_BUFFER_SRC_BUS_SHIFT)) & PACKET_BUFFER_SRC_BUS_MASK)

#define DPE_IDLE_STATUS (0x7U)

#define DPE_VCANINTEN_MASK (DPE_VCANINTEN_VCAN_REC_MASK | DPE_VCANINTEN_VCAN_REC_DROP_MASK | DPE_VCANINTEN_VCAN_SEND_DONE_MASK |\
                            DPE_VCANINTEN_VCAN_SEND_TIMEOUT_MASK | DPE_VCANINTEN_VCAN_SEND_DROP_MASK)
#define DPE_VCANINTSTAT_MASK (DPE_VCANINTSTAT_VCAN_REC_MASK | DPE_VCANINTSTAT_VCAN_REC_DROP_MASK | DPE_VCANINTSTAT_VCAN_SEND_DONE_MASK |\
                            DPE_VCANINTSTAT_VCAN_SEND_TIMEOUT_MASK | DPE_VCANINTSTAT_VCAN_SEND_DROP_MASK)

#define DPE_DIAG_VCANINTEN_MASK (DPE_DVCANINTEN_DVCAN_REC_MASK | DPE_DVCANINTEN_DVCAN_REC_DROP_MASK)
#define DPE_DIAG_VCANINTSTAT_MASK (DPE_DVCANINTSTAT_DVCAN_REC_MASK | DPE_DVCANINTSTAT_DVCAN_REC_DROP_MASK)

#ifdef __cplusplus
}
#endif

#endif /* DPE_IPPRIV_H */
/* End of file */
